R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 1166

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 29 User Break Controller (UBC)
29.2.4
CMAR0 and CMAR1 are readable/writable 32-bit registers which specify the bits to be masked
among the address bits specified by using the match address setting register of the corresponding
channel. (Set the bits to be masked to 1.)
• CAMR0
• CAMR1
Rev.1.00 Dec. 13, 2005 Page 1114 of 1286
REJ09B0158-0100
Bit
31 to 0
Initial value :
Initial value :
Initial value :
Initial value :
R/W:
R/W:
R/W:
R/W:
Bit :
Bit :
Bit :
Bit :
Match Address Mask Setting Registers 0 and 1 (CAMR0 and CAMR1)
Bit Name
CAM
R/W
R/W
R/W
R/W
31
15
31
15
R/W
R/W
R/W
R/W
30
14
30
14
R/W
R/W
R/W
R/W
Initial
Value
Undefined
29
13
29
13
R/W
R/W
R/W
R/W
28
12
28
12
R/W
R/W
R/W
R/W
27
11
27
11
R/W
R/W
R/W
R/W
R/W
R/W
26
10
26
10
Description
Compare Address Mask
Specifies the bits to be masked among the address
bits which are specified using the CAR0 register. (Set
the bits to be masked to 1.)
0: Address bits CA[n] are included in the break
1: Address bits CA[n] are masked and not included in
[n] = any values from 31 to 0
R/W
R/W
R/W
R/W
25
25
9
condition.
the break condition.
9
R/W
R/W
R/W
R/W
24
24
8
8
CAM
CAM
CAM
CAM
R/W
R/W
R/W
R/W
23
23
7
7
R/W
R/W
R/W
R/W
22
22
6
6
R/W
R/W
R/W
R/W
21
21
5
5
R/W
R/W
R/W
R/W
20
20
4
4
R/W
R/W
R/W
R/W
19
19
3
3
R/W
R/W
R/W
R/W
18
18
2
2
R/W
R/W
R/W
R/W
17
17
1
1
R/W
R/W
R/W
R/W
16
16
0
0