R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 1092

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 27 NAND Flash Memory Controller (FLCTL)
27.3.9
FLBSYCNT is a 32-bit read-only register.
The status of flash memory obtained by the status read is stored in the bits STAT[7:0].
The timeout time set in the bits RBTMOUT[19:0] in FLBSYTMR is copied to the bits
RBTIMCNT[19:0] and counting down is started when the FRB pin is placed in a busy state. When
values in the RBTIMCNT[19:0] become 0, 1 is set to the BTOERB bit in FLINTDMACR, thus
notifying that a timeout error has occurred. In this case, an FLSTE interrupt request can be issued
if an interrupt is enabled by the RBERINTE bit in FLINTDMACR.
Rev.1.00 Dec. 13, 2005 Page 1040 of 1286
REJ09B0158-0100
Initial value:
Initial value:
Bit
31 to 24
23 to 20
19 to 0
R/W:
R/W:
Bit:
Bit:
Ready Busy Timeout Counter (FLBSYCNT)
Bit Name
STAT[7:0]
—
RBTIMCNT[19:0] H'00000 R
31
15
R
R
0
0
30
14
R
R
0
0
29
13
R
R
0
0
28
12
STAT[7:0]
R
R
0
0
Initial
Value
H'00
All 0
27
11
R
R
0
0
R/W
R
R
26
10
R
R
0
0
25
R
R
0
9
0
Description
Indicate the flash memory status obtained by the
status read.
Reserved
These bits are always read as 0.
Ready Busy Timeout Counter
When the FRB pin is placed in a busy state, the
values of the bits RBTMOUT[19:0] in FLBSYTMR
are copied to these bits. These bits are counted
down while the FRB pin is busy. A timeout error
occurs when these bits are decremented to 0.
RBTIMCNT[15:0]
24
R
R
0
8
0
23
R
R
0
7
0
22
R
R
0
6
0
21
R
R
0
5
0
20
R
R
0
4
0
19
R
R
0
3
0
RBTIMCNT[19:16]
18
R
R
0
2
0
17
R
R
0
1
0
16
R
R
0
0
0