R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet
R8A77800ANBGAV
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R8A77800ANBGAV Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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SH7780 32 Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH SH7780 Series TM RISC Engine Family R8A77800A Rev.1.00 2005.12 ...
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Rev.1.00 Dec. 13, 2005 Page ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test ...
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Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip ...
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This LSI is a RISC (Reduced Instruction Set Computer) microcomputer which includes a Renesas Technology-original RISC CPU as its core, and the peripheral functions required to configure a system. Target Users: This manual was written for users who will be ...
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Abbreviations ALU Arithmetic Logic Unit ASID Address Space Identifier BGA Ball Grid Array CMT Compare Match Timer (Timer/Counter) CPG Clock Pulse Generator CPU Central Processing Unit DDR Double Data Rate DDRIF DDR-SDRAM Interface DMA Direct Memory Access DMAC Direct Memory ...
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MMCIF Multimedia Card Interface MMU Memory Management Unit MSB Most Significant Bit PC Program Counter PCI Peripheral Component Interconnect PCIC PCI (local bus) Controller RISC Reduced Instruction Set Computer RTC Realtime Clock SCIF Serial Communication Interface with FIFO SIOF Serial ...
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Section 1 Overview................................................................................................1 1.1 SH7780 Features.................................................................................................................... 1 1.2 Block Diagram ....................................................................................................................... 9 1.3 Pin Arrangement .................................................................................................................. 10 1.4 Pin Functions ....................................................................................................................... 11 1.5 Memory Address Map ......................................................................................................... 27 1.6 SuperHyway Bus ................................................................................................................. 30 1.7 SuperHyway Memory (SuperHyway RAM)........................................................................ 31 Section ...
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Register Descriptions........................................................................................................... 97 5.2.1 TRAPA Exception Register (TRA) ........................................................................ 98 5.2.2 Exception Event Register (EXPEVT)..................................................................... 99 5.2.3 Interrupt Event Register (INTEVT)...................................................................... 100 5.3 Exception Handling Functions........................................................................................... 101 5.3.1 Exception Handling Flow ..................................................................................... 101 5.3.2 Exception Handling Vector Addresses ................................................................. ...
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Section 7 Memory Management Unit (MMU) ..................................................147 7.1 Overview of MMU ............................................................................................................ 147 7.1.1 Address Spaces ..................................................................................................... 149 7.2 Register Descriptions ......................................................................................................... 156 7.2.1 Page Table Entry High Register (PTEH) .............................................................. 157 7.2.2 Page Table Entry Low Register (PTEL) ............................................................... ...
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Memory-Mapped PMB Configuration.................................................................. 192 7.7.6 Notes on Using 32-Bit Address Extended Mode .................................................. 194 Section 8 Caches................................................................................................ 197 8.1 Features.............................................................................................................................. 197 8.2 Register Descriptions......................................................................................................... 200 8.2.1 Cache Control Register (CCR) ............................................................................. 201 8.2.2 Queue Address Control Register 0 (QACR0)....................................................... ...
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On-Chip Memory Control Register (RAMCR) .................................................... 229 9.2.2 L Memory Transfer Source Address Register 0 (LSA0) ...................................... 230 9.2.3 L Memory Transfer Source Address Register 1 (LSA1) ...................................... 232 9.2.4 L Memory Transfer Destination Address Register 0 (LDA0) .............................. ...
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IRL Interrupts ....................................................................................................... 297 10.4.4 On-chip Module Interrupts ................................................................................... 299 10.4.5 Interrupt Priority Levels of On-chip Module Interrupts ....................................... 300 10.4.6 Interrupt Exception Handling and Priority............................................................ 301 10.5 Operation ........................................................................................................................... 308 10.5.1 Interrupt Sequence ................................................................................................ 308 10.5.2 Multiple Interrupts ...
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Section 12 DDR-SDRAM Interface (DDRIF)...................................................401 12.1 Features.............................................................................................................................. 401 12.2 Input/Output Pins ............................................................................................................... 403 12.3 Address Space, Bus Width, and Data Alignment............................................................... 404 12.3.1 Address Space of the DDRIF................................................................................ 404 12.3.2 Memory Data Bus Width ...................................................................................... 405 12.3.3 Data Alignment..................................................................................................... 406 ...
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Target Access........................................................................................................ 532 13.4.5 Host Bus Bridge Mode ......................................................................................... 541 13.4.6 Normal mode ........................................................................................................ 544 13.4.7 Power Management .............................................................................................. 544 13.4.8 PCI Local Bus Basic Interface.............................................................................. 545 Section 14 Direct Memory Access Controller (DMAC)................................... 557 14.1 Features.............................................................................................................................. 557 14.2 ...
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Section 15 Clock Pulse Generator (CPG)..........................................................613 15.1 Features.............................................................................................................................. 613 15.2 Input/Output Pins ............................................................................................................... 616 15.3 Clock Operating Modes ..................................................................................................... 617 15.4 Register Descriptions ......................................................................................................... 618 15.4.1 Frequency Control Register (FRQCR) ................................................................. 619 15.4.2 PLL Control Register (PLLCR)............................................................................ 621 15.5 Notes ...
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Module Standby State ........................................................................................................ 649 17.5.1 Transition to Module Standby Mode .................................................................... 649 17.5.2 Cancellation of Module Standby Mode and Resume............................................ 649 17.6 DDR-SDRAM Power Supply Backup............................................................................... 650 17.6.1 Self-Refresh and Initialization .............................................................................. 650 17.6.2 DDR-SDRAM Backup Sequence when ...
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Control Register (CMTCTL) ................................................................................ 684 19.3.4 Interrupt Status Register (CMTIRQS) .................................................................. 688 19.3.5 Channels Time Registers (CMTCH0T to CMTCH3T)............................... 689 19.3.6 Channels Stop Time Registers (CMTCH0ST to CMTCH1ST).................. 689 19.3.7 Channels 0 to ...
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Operation ........................................................................................................................... 727 20.4.1 Time Setting Procedures....................................................................................... 727 20.4.2 Time Reading Procedures..................................................................................... 728 20.4.3 Alarm Function..................................................................................................... 729 20.5 Interrupts............................................................................................................................ 730 20.6 Usage Notes ....................................................................................................................... 730 20.6.1 Register Initialization............................................................................................ 730 20.6.2 Crystal Oscillator Circuit ...................................................................................... 730 20.6.3 Interrupt source and ...
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Clock Select Register (SISCR) ............................................................................. 804 22.3.3 Control Register (SICTR) ..................................................................................... 806 22.3.4 Transmit Data Register (SITDR) .......................................................................... 809 22.3.5 Receive Data Register (SIRDR) ........................................................................... 810 22.3.6 Transmit Control Data Register (SITCR) ............................................................. 811 22.3.7 Receive Control Data Register ...
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Section 24 Multimedia Card Interface (MMCIF) ............................................. 865 24.1 Features.............................................................................................................................. 865 24.2 Input/Output Pins............................................................................................................... 866 24.3 Register Descriptions......................................................................................................... 867 24.3.1 Command Registers (CMDR0 to CMDR5)................................................ 871 24.3.2 Command Start Register (CMDSTRT) ................................................................ 872 24.3.3 Operation Control Register ...
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TX Status Register (HACTSR)............................................................................. 967 25.3.8 RX Interrupt Enable Register (HACRIER)........................................................... 969 25.3.9 RX Status Register (HACRSR) ............................................................................ 970 25.3.10 HAC Control Register (HACACR) ...................................................................... 971 25 Frame Slot Structure............................................................................................... 973 25.5 Operation ........................................................................................................................... 974 25.5.1 Receiver ...
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Address Register (FLADR) ................................................................................ 1030 27.3.5 Data Counter Register (FLDTCNTR) ................................................................ 1032 27.3.6 Data Register (FLDATAR) ................................................................................ 1033 27.3.7 Interrupt DMA Control Register (FLINTDMACR) ........................................... 1034 27.3.8 Ready Busy Timeout Setting Register (FLBSYTMR) ....................................... 1039 27.3.9 Ready Busy Timeout ...
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Port G Data Register (PGDR)............................................................................. 1084 28.2.20 Port H Data Register (PHDR)............................................................................. 1085 28.2.21 Port J Data Register (PJDR) ............................................................................... 1085 28.2.22 Port K Data Register (PKDR)............................................................................. 1086 28.2.23 Port L Data Register (PLDR).............................................................................. 1086 28.2.24 Port M Data ...
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Usage Notes ..................................................................................................................... 1132 Section 30 User Debugging Interface (H-UDI)............................................... 1135 30.1 Features............................................................................................................................ 1135 30.2 Input/Output Pins............................................................................................................. 1137 30.3 Boundary Scan TAP Controllers (IDCODE, EXTEST, SAMPLE/PRELOAD, and BYPASS) .......................................... 1138 30.4 Register Descriptions....................................................................................................... 1140 30.4.1 Instruction Register (SDIR) ................................................................................ ...
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AC Characteristic Test Conditions................................................................................... 1214 31.5 Change in Delay Time Based on Load Capacitance ........................................................ 1215 Appendix ..........................................................................................................1217 A. CPU Operation Mode Register (CPUOPM) .................................................................... 1217 B. Instruction Prefetching and Its Side Effects..................................................................... 1219 C. Speculative Execution for Subroutine ...
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Rev.1.00 Dec. 13, 2005 Page xxviii of l ...
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Section 1 Overview Figure 1.1 SH7780 Block Diagram ................................................................................................ 9 Figure 1.2 SH7780 Pin Arrangement............................................................................................ 10 Figure 1.3 Physical Address Space of SH7780............................................................................. 28 Figure 1.4 Relationship between AREASEL Bits and Memory Address Map............................. 29 Section 2 Programming Model Figure ...
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Section 7 Memory Management Unit (MMU) Figure 7.1 Role of MMU............................................................................................................ 149 Figure 7.2 Virtual Address Space (AT in MMUCR = 0)............................................................ 150 Figure 7.3 Virtual Address Space (AT in MMUCR = 1)............................................................ 151 Figure 7.4 P4 Area...................................................................................................................... 153 Figure ...
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Figure 11.2 Correspondence between Virtual Address Space and External Memory Space of LBSC........................................................................................................ 321 Figure 11.3 External Memory Space Allocation (29-bit address mode)..................................... 323 Figure 11.4 Basic Timing of SRAM Interface............................................................................ 362 Figure 11.5 Example of 32-Bit Data-Width SRAM Connection ...
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Figure 11.34 Wait Cycles between Access Cycles ..................................................................... 394 Figure 11.35 Arbitration Sequence............................................................................................. 396 Figure 11.36 Example of the Bus Release Restraint by the DMAC CHCR LCKN bit .............. 398 Section 12 DDR-SDRAM Interface (DDRIF) Figure 12.1 DDRIF Block Diagram ...
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Figure 13.11 PCI Local Bus to SuperHyway Bus Address Translation (PCIC I/O Space) ........ 535 Figure 13.12 Endian Conversion from PCI Local Bus to SuperHyway bus (Non-Byte Swapping: TBS = 0) ............................................................................ 537 Figure 13.13 Endian Conversion from PCI Local ...
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Section 15 Clock Pulse Generator (CPG) Figure 15.1 Block Diagram of CPG ........................................................................................... 614 Figure 15.2 Points for Attention when Using Crystal Resonator................................................ 622 Figure 15.3 Points for Attention when Using PLL and DLL Circuit.......................................... 623 Section 16 Watchdog Timer ...
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Figure 19.5 CMT_CTRn Assert Timing (channel 0 and 1) ........................................................ 694 Figure 19.6 32-Bit Timer Mode: Output Compare (channel 1 and channel 0) ........................... 694 Figure 19.7 32-bit Timer Mode: Output Compare Operation Timing (Example of High output in Active ...
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Figure 21.12 Sample Serial Reception Flowchart (2)................................................................. 780 Figure 21.13 Sample SCIF Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit) .................................................. 782 Figure 21.14 Sample Operation Using Modem Control (SCIF0_RTS) (Only in Channel 0)..... 782 Figure 21.15 Data ...
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Figure 23.4 Timing Conditions when FBS = 1........................................................................... 864 Section 24 Multimedia Card Interface (MMCIF) Figure 24.1 Block Diagram of MMCIF...................................................................................... 866 Figure 24.2 DR Access Example ................................................................................................ 899 Figure 24.3 Example of Command Sequence for Commands Not Requiring Command ...
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Figure 24.18 Example of Command Sequence for Commands with Write Data (Stream Transfer)................................................................................................... 924 Figure 24.19 Example of Operational Flow for Commands with Write Data (Single Block Transfer) ......................................................................................... 925 Figure 24.20 Example of Operational Flow for Commands with Write ...
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Figure 25.5 Sample Flowchart for Off-Chip Codec Register Read (1) ...................................... 978 Figure 25.6 Sample Flowchart for Off-Chip Codec Register Read (2) ...................................... 979 Figure 25.7 Sample Flowchart for Off-Chip Codec Register Read (3) ...................................... 980 Section 26 Serial Sound ...
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Figure 27.7 Sector Access when Unusable Sector Exists in Continuous Sectors..................... 1048 Figure 27.8 NAND Flash Command Access (Block Erase)..................................................... 1050 Figure 27.9 NAND Flash Sector Access (Flash Write) Using DMA ....................................... 1051 Figure 27.10 NAND Flash Command Access (Flash ...
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Figure 31.18 PCMCIA I/O Bus Cycle (TEDx = 1, THEx = 1, IW/PCIW = 1, One Internal Wait, Dynamic Bus Sizing).................................... 1175 Figure 31.19 MPX Basic Bus Cycle: Read............................................................................... 1176 Figure 31.20 MPX Basic Bus Cycle: Write.............................................................................. 1177 Figure 31.21 ...
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Figure 31.56 SSI Receive Timing (2)....................................................................................... 1206 Figure 31.57 Command Issue Timing of NAND-type Flash Memory ..................................... 1208 Figure 31.58 Address Issue Timing of NAND-type Flash Memory......................................... 1209 Figure 31.59 Data Read Timing of NAND-type Flash Memory .............................................. 1209 Figure ...
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Section 1 Overview Table 1.1 SH7780 Features....................................................................................................... 2 Table 1.2 Pin Functions .......................................................................................................... 11 Section 2 Programming Model Table 2.1 Initial Register Values............................................................................................. 35 Table 2.2 Bit Allocation for FPU Exception Handling........................................................... 45 Section 3 Instruction Set Table 3.1 Execution ...
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Section 7 Memory Management Unit (MMU) Table 7.1 Register Configuration.......................................................................................... 156 Table 7.2 Register States in Each Processing State .............................................................. 156 Section 8 Caches Table 8.1 Cache Features...................................................................................................... 197 Table 8.2 Store Queue Features ............................................................................................ 197 Table 8.3 Register Configuration.......................................................................................... ...
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Table 11.10 16-Bit External Device/Big-Endian Access and Data Alignment..................... 353 Table 11.11 8-Bit External Device/Big-Endian Access and Data Alignment....................... 354 Table 11.12 32-Bit External Device/Little-Endian Access and Data Alignment.................. 355 Table 11.13 16-Bit External Device/Little-Endian Access and Data Alignment.................. 355 ...
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Section 15 Clock Pulse Generator (CPG) Table 15.1 CPG Pin Configuration......................................................................................... 616 Table 15.2 Clock Operating Modes ........................................................................................ 617 Table 15.3 Register configuration........................................................................................... 618 Table 15.4 Register States of CPG in Each Processing Mode ................................................ 618 Section 16 Watchdog Timer ...
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Section 21 Serial Communication Interface with FIFO (SCIF) Table 21.1 Pin Configuration.................................................................................................. 739 Table 21.2 Register Configuration.......................................................................................... 740 Table 21.3 Register States of SCIF in Each Processing Mode ............................................... 741 Table 21.4 SCSMR Settings ................................................................................................... 758 Table 21.5 SCSMR Settings ...
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Section 25 Audio Codec Interface (HAC) Table 25.1 Pin Configuration.................................................................................................. 956 Table 25.2 Register Configuration.......................................................................................... 957 Table 25.3 Register States of HAC in Each Processing Mode ............................................... 957 Table 25.4 AC97 Transmit Frame Structure........................................................................... 973 Table 25.5 AC97 Receive Frame ...
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Table 31.2 DC Characteristics (T Table 31.3 Permissible Output Currents ............................................................................... 1159 Table 31.4 Clock Timing ...................................................................................................... 1159 Table 31.5 Clock and Control Signal Timing ....................................................................... 1160 Table 31.6 Control Signal Timing ........................................................................................ 1163 Table 31.7 Bus Timing ......................................................................................................... 1164 ...
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Rev.1.00 Dec. 13, 2005 Page ...
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SH7780 Features The SH7780 is an integrated system-on-a-chip microprocessor that is designed as a high performance, embedded, stand-alone Host Processor aimed at the multimedia, infotainment and consumer networking market. The SH7780 features a DDR-SDRAM interface that can be coupled ...
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Section 1 Overview Table 1.1 SH7780 Features Item Features • LSI Operating frequency: 400 MHz • Performance: 720MIPS, 2.8 GFLOPS • Voltage: 1.25 V (internal), 2.5 V (DDR-SDRAM interface), 3.3 V (I/O) • Superscalar architecture: Parallel execution of two instructions ...
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Item Features • FPU On-chip floating-point coprocessor • Supports single-precision (32 bits) and double-precision (64 bits) • Supports IEEE754-compliant data types and exceptions • Two rounding modes: Round to Nearest and Round to Zero • Handling of denormalized numbers: Truncation ...
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Section 1 Overview Item Features • Memory 4 Gbytes of physical address space, 256 address space identifiers management (address space identifier ASID: 8 bits) unit (MMU) • Supports single virtual memory mode and multiple virtual memory mode • Supports multiple ...
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Item Features • Interrupt controller Nine independent external interrupts: NMI and IRQ7 to IRQ0 (INTC) NMI: Fall/rise selectable IRQ: Fall/rise/high level/low level selectable 15-level signed external interrupts: IRL3 to IRL0, or IRL7 to IRL4 • • On-chip module ...
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Section 1 Overview Item Features • PCI bus controller PCI bus controller (subset of revision 2.2) (PCIC) 32-bit bus 33 MHz/66 MHz support • PCI master/target support • PCI host function support Built-in bus arbiter • Interrupt ...
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Item Features • Timer unit (TMU) 6-channel auto-reload 32-bit timer • Input-capture function (only channel 2) • Choice of seven types counter input clocks (external and peripheral clocks) • Compare Match 4-channel auto-reload 32-bit timers Timer (CMT) • Choice of ...
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Section 1 Overview Item Features • Audio codec Digital interface for audio codec interface (HAC) • Supports transfer for slot 1 to slot 4 • Choice of 16- or 20-bit DMA transfer • Supports various sampling rates by adjusting slot ...
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Block Diagram CPU FPU UBC AUD SH-4A core [Legend] AUD: Advanced user debugger CMT: Timer/counter CPG: Clock pulse generator CPU: Central processing unit DDRIF: DDR-SDRAM interface DMAC: Direct memory access controller FLCTL: NAND flash memory controller FPU: Floating-point unit ...
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Section 1 Overview 1.3 Pin Arrangement Rev.1.00 Dec. 13, 2005 Page 10 of 1286 REJ09B0158-0100 Figure 1.2 SH7780 Pin Arrangement ...
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Pin Functions Table 1.2 lists the pin functions of the SH7780. In the I/O column and IO indicate input, output, and input/output, respectively. In the GPIO column, for example, A0 indicates the port A0, which also functions ...
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Section 1 Overview Pin No. No. Pin Name 21 A21 SCIF1_TXD/MCCLK/MODE5 22 A22 XTAL2 23 A23 EXTAL2 24 A24 VDD-RTC 25 A25 VSS-RTC 26 B1 VSSQ-DDR 27 B2 VCCQ-DDR BKPRST CKE 30 B5 MA13 MCAS 31 ...
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Pin No. No. Pin Name 47 B22 SCIF0_RXD/HSPI_RX/FRB 48 B23 TCLK/IOIS16 XRTCSTBI 49 B24 50 B25 VSSQ 51 C1 MDA0 52 C2 VCCQ-DDR 53 C3 VSSQ-DDR 54 C4 VCCQ-DDR 55 C5 MA12 56 C6 MA11 57 C7 MA9 58 C8 ...
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Section 1 Overview Pin No. No. Pin Name 72 C22 SCIF0_TXD/HSPI_TX/FWE/MODE8 O/O/O/I SCIF0 transmit data/HSPI transmit 73 C23 SCIF0_SCK/HSPI_CLK/FRE 74 C24 VDDQ 75 C25 IRQ/IRL7/FD7 76 D1 MDA1 77 D2 MDA16 78 D3 VSSQ-DDR 79 D4 VCCQ-DDR 80 D5 VSSQ-DDR ...
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Pin No. No. Pin Name 98 D23 VDD 99 D24 IRQ/IRL6/FD6/MODE6 100 D25 IRQ/IRL5/FD5/MODE4 101 E1 MDA2 102 E2 MDA17 103 E3 MDA18 104 E4 VCCQ-DDR 105 E5 VSSQ-DDR 106 E6 VSSQ-DDR 107 E7 VCCQ-DDR 108 E8 VDD 109 E9 ...
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Section 1 Overview Pin No. No. Pin Name 126 F1 MDA3 127 F2 MDA19 128 F3 MDA20 129 F4 VCCQ-DDR 130 F5 VSSQ-DDR 131 F21 VDDQ 132 F22 VDDQ 133 F23 IRQ/IRL1 134 F24 IRQ/IRL0 135 F25 NMI 136 G1 ...
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Pin No. No. Pin Name 156 J1 MDA7 157 J2 MDA6 158 J3 MDQM2 159 J4 VDD-DLL1 160 J5 VSS-DLL1 161 J21 VDD 162 J22 AD10 163 J23 AD12 164 J24 AD6 165 J25 CBE0 166 K1 MDQM0 167 K2 ...
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Section 1 Overview Pin No. No. Pin Name 185 L3 MDQM3 186 L4 VDD 187 L5 VSS 188 L10 VSS 189 L11 VSS 190 L12 VSS 191 L13 VSSQ 192 L14 VSS 193 L15 VSS 194 L16 VSS 195 L21 ...
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Pin No. No. Pin Name 215 M24 PAR STOP 216 M25 217 N1 MDA9 218 N2 MDA26 219 N3 MDA27 220 N4 VSSQ-DDR 221 N5 VSSQ-DDR 222 N10 VSS 223 N11 VSS 224 N12 VSSQ-DDR 225 N13 VSSQ 226 N14 ...
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Section 1 Overview Pin No. No. Pin Name 245 P16 VSS 246 P21 VDD 247 P22 AD17 248 P23 AD19 249 P24 AD16 250 P25 AD18 251 R1 MDA11 252 R2 MDA30 253 R3 MDA31 254 R4 VCCQ-DDR 255 R5 ...
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Pin No. No. Pin Name 275 T12 VSS 276 T13 VSS 277 T14 VSS 278 T15 VSS 279 T16 VSS 280 T21 VDD 281 T22 CBE3 282 T23 AD25 283 T24 IDSEL 284 T25 AD24 285 U1 MDA15 286 U2 ...
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Section 1 Overview Pin No. No. Pin Name 305 W1 A25 306 W2 STATUS0/CMT_CTR0 307 W3 STATUS1/CMT_CTR1 308 W4 VDD 309 W5 VDD 310 W21 VSS REQ2 311 W22 REQ1 312 W23 GNT2 313 W24 GNT1 314 W25 315 Y1 ...
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Pin No. No. Pin Name 334 AA10 VSS 335 AA11 VDD 336 AA12 VDDQ 337 AA13 VSSQ 338 AA14 VSSQ 339 AA15 VDD 340 AA16 VSS 341 AA17 VDDQ 342 AA18 VDDQ 343 AA19 VSSQ 344 AA20 VSSQ 345 AA21 ...
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Section 1 Overview Pin No. No. Pin Name 364 AB15 VDDQ 365 AB16 VSSQ AB17 BACK 366 AB18 CS4 367 AB19 CS6 368 369 AB20 VSS-PLL3 370 AB21 VDD 371 AB22 VDDQ 372 AB23 VDDQ 373 AB24 VSS 374 AB25 ...
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Pin No. No. Pin Name AC20 CS1 394 395 AC21 VSS-PLL2 396 AC22 VDD 397 AC23 VDDQ 398 AC24 VDDQ 399 AC25 MPMD 400 AD1 A13 401 AD2 VDDQ 402 AD3 A11 403 AD4 A8 404 AD5 A4 405 AD6 ...
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Section 1 Overview Pin No. No. Pin Name 424 AD25 VSSQ 425 AE1 VSSQ 426 AE2 A12 427 AE3 A10 428 AE4 A7 429 AE5 A3 430 AE6 D31 431 AE7 D27 WE3/IOWR 432 AE8 433 AE9 D20 434 AE10 ...
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Memory Address Map The SH7780 supports 32-bit virtual address space, and supports both 29-bit and 32-bit physical address spaces (normal mode and extended mode). For details of mappings from the virtual address space to the physical address spaces, see ...
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Section 1 Overview H'0000 0000 Area 0 (LBSC) H'0400 0000 Area 1 (LBSC) H'0800 0000 Area 2 (LBSC/DDRIF) H'0C00 0000 Area 3 (DDRIF) H'1000 0000 Area 4 (LBSC/DDRIF/PCIC) H'1400 0000 Area 5 (LBSC/DDRIF) H'1800 0000 Area 6 (LBSC) H'1C00 0000 ...
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MMSELR.AREASEL[2:0]* H'0000 0000 Area 0 (LBSC) H'0400 0000 Area 1 (LBSC) H'0800 0000 Area 2 (LBSC/DDRIF) H'0C00 0000 Area 3 (DDRIF) H'1000 0000 Area 4 (LBSC/DDRIF/PCIC) H'1400 0000 Area 5 (LBSC/DDRIF) H'1800 0000 Area 6 (LBSC) H'1C00 0000 Area 7 ...
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Section 1 Overview 1.6 SuperHyway Bus The SH7780 is implemented with the SuperHyway bus as the system bus. The SuperHyway bus is a 32-bit-address, 64-bit-data internal bus capable 200 MHz operation that is connected to on-chip modules ...
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SuperHyway Memory (SuperHyway RAM) The SH7780 includes an on-chip SuperHyway memory which stores instructions or data. The SuperHyway memory has the following features. • Capacity Total SuperHyway memory capacity is 32 Kbytes (512 words • Memory address map The ...
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Section 1 Overview Rev.1.00 Dec. 13, 2005 Page 32 of 1286 REJ09B0158-0100 ...
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Section 2 Programming Model The programming model of this LSI is explained in this section. This LSI has registers and data formats as shown below. 2.1 Data Formats The data formats supported in this LSI are shown in figure 2.1. ...
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Section 2 Programming Model 2.2 Register Descriptions 2.2.1 Privileged Mode and Banks Processing Modes: This LSI has two processing modes, user mode and privileged mode. This LSI normally operates in user mode, and switches to privileged mode when an exception ...
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Floating-Point Registers and System Registers Related to FPU: There are thirty-two floating- point registers, FR0–FR15 and XF0–XF15. FR0–FR15 and XF0–XF15 can be assigned to either of two banks (FPR0_BANK0–FPR15_BANK0 or FPR0_BANK1–FPR15_BANK1). FR0–FR15 can be used as the eight registers DR0/2/4/6/8/10/12/14 ...
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Section 2 Programming Model BANK0 BANK0 BANK0 BANK0 BANK0 BANK0 BANK0 BANK0 ...
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General Registers Figure 2.3 shows the relationship between the processing modes and general registers. This LSI has twenty-four 32-bit general registers (R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BANK1, and R8 to R15). However, only 16 of these can be accessed ...
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Section 2 Programming Model Note on Programming: As the user are assigned to R0_BANK0 to R7_BANK0, and after an exception or interrupt are assigned to R0_BANK1 to R7_BANK1 not necessary for the ...
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Single-precision floating-point extended register matrix, XMTRX: XMTRX comprises all 16 XF registers. XMTRX = XF0 XF4 XF1 XF5 XF2 XF6 XF3 XF7 FPSCR.FR=0 FV0 DR0 FR0 FR1 DR2 FR2 FR3 FV4 DR4 FR4 FR5 DR6 FR6 FR7 FV8 DR8 ...
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Section 2 Programming Model 2.2.4 Control Registers Status Register (SR): BIt Initial value R/W: R R/W R/W R/W BIt Initial value R/W: R/W R ...
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Initial Bit Bit Name Value — All — All IMASK All — All ...
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Section 2 Programming Model Saved Status Register (SSR) (32 bits, Privileged Mode, Initial Value = Undefined): The contents of SR are saved to SSR in the event of an exception or interrupt. Saved Program Counter (SPC) (32 bits, Privileged Mode, ...
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Floating-Point Status/Control Register (FPSCR) BIt Initial value R/ BIt Cause Initial value R/W: R/W R/W R/W R/W Initial Bit Bit Name Value ...
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Section 2 Programming Model Initial Bit Bit Name Value Cause All Enable (EN) All Flag All Rev.1.00 Dec. 13, 2005 Page 44 of 1286 ...
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Floating-point register 63 FR (2i) 63 Memory area 8n <Little endian> 63 Floating-point register 63 FR (2i) 63 Memory area 4n+3 Notes the case and register can ...
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Section 2 Programming Model 2.3 Memory-Mapped Registers Some control registers are mapped to the following memory areas. Each of the mapped registers has two addresses. H'1C00 0000 to H'1FFF FFFF H'FC00 0000 to H'FFFF FFFF These two areas are used ...
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Data Formats in Registers Register operands are always longwords (32 bits). When a memory operand is only a byte (8 bits word (16 bits sign-extended into a longword when loaded into a register ...
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Section 2 Programming Model 2.5 Data Formats in Memory Memory data formats are classified into bytes, words, and longwords. Memory can be accessed in an 8-bit byte, 16-bit word, or 32-bit longword form. A memory operand less than 32 bits ...
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Processing States This LSI has major three processing states: the reset state, instruction execution state, and power- down state. Reset State: In this state the CPU is reset. The reset state is divided into the power-on reset state and ...
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Section 2 Programming Model 2.7 Usage Note 2.7.1 Notes on self-modified codes* This LSI prefetches instructions more drastically than conventional SH-4 to accelerate the processing speed. Therefore if the instruction in the memory is modified and it is executed immediately, ...
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Section 3 Instruction Set This LSI's instruction set is implemented with 16-bit fixed-length instructions. This LSI can use byte (8-bit), word (16-bit), longword (32-bit), and quadword (64-bit) data sizes for memory access. Single-precision floating-point data (32 bits) can be moved ...
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Section 3 Instruction Set T Bit: The T bit used to show the result of a compare operation, and is referenced by a conditional branch instruction. An example of the use of a conditional branch instruction is ...
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Addressing Modes Addressing modes and effective address calculation methods are shown in table 3.2. When a location in virtual memory space is accessed (AT in MMUCR = 1), the effective address is translated into a physical memory address. If ...
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Section 3 Instruction Set Addressing Instruction Mode Format Register @(disp:4, Rn) indirect with displacement Indexed @(R0, Rn) register indirect GBR indirect @(disp:8, GBR) Effective address is register GBR contents with with displace- ment Indexed GBR @(R0, GBR) indirect Rev.1.00 Dec. ...
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Addressing Instruction Mode Format PC-relative @(disp:8, PC) Effective address with 8-bit displacement with displacement PC-relative disp:8 Effective Address Calculation Method disp added. After disp is zero-extended multiplied by 2 (word (longword), according ...
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Section 3 Instruction Set Addressing Instruction Mode Format PC-relative disp:12 Rn Immediate #imm:8 #imm:8 #imm:8 Note: For the addressing modes below that use a displacement (disp), the assembler descriptions in this manual show the value before scaling (×1, ×2, or ...
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Instruction Set Table 3.3 shows the notation used in the SH instruction lists shown in tables 3.4 to 3.13. Table 3.3 Notation Used in Instruction List Item Format Instruction OP.Sz SRC, DEST mnemonic Operation notation MSB ↔ LSB Instruction ...
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Section 3 Instruction Set Item Format Privileged mode T bit Value of T bit after instruction execution New Note: Scaling (×1, ×2, ×4, or ×8) is executed according to the size of the instruction operand. Rev.1.00 Dec. 13, 2005 ...
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Table 3.4 Fixed-Point Transfer Instructions Instruction Operation imm → sign extension → Rn #imm,Rn MOV (disp × → sign MOV.W @(disp*,PC),Rn extension → Rn (disp × & H'FFFF FFFC MOV.L @(disp*,PC),Rn + ...
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Section 3 Instruction Set Instruction Operation (R0 + Rm) → MOV.W @(R0,Rm),Rn sign extension → Rn (R0 + Rm) → Rn MOV.L @(R0,Rm),Rn R0 → (disp + GBR) MOV.B R0,@(disp*,GBR) R0 → (disp × GBR) MOV.W R0,@(disp*,GBR) R0 ...
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Table 3.5 Arithmetic Operation Instructions Instruction Operation → Rn ADD Rm,Rn #imm, imm → Rn ADD → Rn, ADDC Rm,Rn carry → → Rn, ADDV Rm,Rn ...
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Section 3 Instruction Set Instruction Operation DMULU.L Rm,Rn Unsigned, Rn × Rm → MAC, 32 × 32 → 64 bits Rn – 1 → Rn when → T When Rn ≠ → ...
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Table 3.6 Logic Operation Instructions Instruction Operation Rn & Rm → Rn AND Rm,Rn R0 & imm → R0 AND #imm,R0 AND.B (R0 + GBR) & imm #imm,@(R0,GBR) → (R0 + GBR) ~Rm → Rn NOT Rm, ...
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Section 3 Instruction Set Table 3.7 Shift Instructions Instruction Operation T ← Rn ← MSB ROTL Rn LSB → Rn → T ROTR Rn T ← Rn ← T ROTCL Rn T → Rn → T ROTCR Rn When Rm ...
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Table 3.8 Branch Instructions Instruction Operation When disp × label 4 → PC When nop BF/S label Delayed branch; when disp × ...
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Section 3 Instruction Set Table 3.9 System Control Instructions Instruction Operation 0 → MACH, MACL CLRMAC 0 → S CLRS 0 → T CLRT ICBI @Rn Invalidates instruction cache block indicated by virtual address Rm → SR LDC Rm,SR Rm ...
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Instruction Operation NOP No operation OCBI @Rn Invalidates operand cache block OCBP @Rn Writes back and invalidates operand cache block OCBWB @Rn Writes back operand cache block (Rn) → operand cache PREF @Rn PREFI @Rn Reads 32-byte instruction block into ...
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Section 3 Instruction Set Instruction Operation PR → Rn STS PR,Rn Rn – 4 → Rn, MACH → (Rn) 0100nnnn00000010 STS.L MACH,@-Rn Rn – 4 → Rn, MACL → (Rn) STS.L MACL,@-Rn Rn – 4 → Rn, PR → (Rn) ...
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Table 3.10 Floating-Point Single-Precision Instructions Instruction Operation H'0000 0000 → FRn FLDI0 FRn H'3F80 0000 → FRn FLDI1 FRn FRm → FRn FMOV FRm,FRn (Rm) → FRn FMOV.S @Rm,FRn @(R0,Rm),FRn (R0 + Rm) → FRn FMOV.S (Rm) → FRn, Rm ...
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Section 3 Instruction Set Table 3.11 Floating-Point Double-Precision Instructions Instruction Operation FABS DRn DRn & H'7FFF FFFF FFFF FFFF → DRn DRn + DRm → DRn FADD DRm,DRn When DRn = DRm, 1 → T FCMP/EQ DRm,DRn Otherwise, 0 → ...
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Table 3.13 Floating-Point Graphics Acceleration Instructions Instruction Operation DRm → XDn FMOV DRm,XDn XDm → DRn FMOV XDm,DRn XDm → XDn FMOV XDm,XDn (Rm) → XDn FMOV @Rm,XDn (Rm) → XDn → Rm FMOV @Rm+,XDn @(R0,Rm),XDn (R0 ...
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Section 3 Instruction Set Rev.1.00 Dec. 13, 2005 Page 72 of 1286 REJ09B0158-0100 ...
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This LSI is a 2-ILP (instruction-level-parallelism) superscalar pipelining microprocessor. Instruction execution is pipelined, and two instructions can be executed in parallel. 4.1 Pipelines Figure 4.1 shows the basic pipelines. Normally, a pipeline consists of seven stages: instruction sfetch (I1/I2), decode ...
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Section 4 Pipelining Figure 4.2 shows the instruction execution patterns. Representations in figure 4.2 and their descriptions are listed in table 4.1. Table 4.1 Representations of Instruction Execution Patterns Representation ...
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BF, BF/S, BT, BT/S, BRA, BSR E1/S1 (I1) (1-2) JSR, JMP, BRAF, BSRF: 1 issue cycle + 3 branch cycles E1/S1 1 issue cycle ...
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Section 4 Pipelining (2-1) 1-step operation (EX type): 1 issue cycle EXT[SU].[BW], MOVT, SWAP, XTRCT, ADD*, CMP*, DIV*, DT, NEG*, SUB*, AND, AND#, NOT, OR, OR#, TST, TST#, XOR, XOR#, ROT*, SHA*, SHL*, CLRS, CLRT, SETS, SETT Note: Except for ...
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Load/store: 1 issue cycle MOV.[BWL], MOV.[BWL] @(d,GBR (3-2) AND.B, OR.B, XOR.B, TST.B: 3 issue cycles (3-3) TAS.B: 4 issue cycles (3-4) PREF, OCBI, OCBP, OCBWB, ...
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Section 4 Pipelining (4-1) LDC to Rp_BANK/SSR/SPC/VBR: 1 issue cycle I1 I2 (4-2) LDC to DBR/SGR: 4 issue cycles I1 I2 (4-3) LDC to GBR: 1 issue cycle I1 I2 (4-4) LDC to SR: 4 issue cycles + 3 branch ...
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STC from DBR/GBR/Rp_BANK/SSR/SPC/VBR/SGR: 1 issue cycle (4-10) STC from SR: 1 issue cycle E1s1 (4-11) STC.L from DBR/GBR/Rp_BANK/SSR/SPC/VBR/SGR: 1 issue cycle (4-12) STC.L from SR: 1 issue cycle ...
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Section 4 Pipelining (5-1) LDS to MACH/L: 1 issue cycle I1 I2 (5-2) LDS.L to MACH/L: 1 issue cycle I1 I2 (5-3) STS from MACH/L: 1 issue cycle I1 I2 (5-4) STS.L from MACH/L: 1 issue cycle I1 I2 (5-5) ...
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LDS to FPUL: 1 issue cycle FS1 (6-2) STS from FPUL: 1 issue cycle FS1 s1 (6-3) LDS.L to FPUL: 1 issue cycle FS1 (6-4) STS.L from FPUL: ...
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Section 4 Pipelining (6-12) Single-precision FABS, FNEG/double-precision FABS, FNEG: 1 issue cycle (6-13) FLDI0, FLDI1: 1 issue cycle (6-14) Single-precision floating-point computation: 1 issue cycle FCMP/EQ, FCMP/GT, FADD, FLOAT, FMAC, FMUL, FSUB, FTRC, FRCHG, ...
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FIPR: 1 issue cycle FE1 (6-20) FTRV: 1 issue cycle FE1 (6-21) FSRRA: 1 issue cycle FE1 (6-22) FSCA: 1 issue cycle FE1 Figure 4.2 Instruction Execution ...
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Section 4 Pipelining 4.2 Parallel-Executability Instructions are categorized into six groups according to the internal function blocks used, as shown in table 4.2. Table 4.3 shows the parallel-executability of pairs of instructions in terms of groups. For example, ADD in ...
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Instruction Group FE FADD FSUB FCMP (S/D) FCNVDS FCNVSD CO AND.B #imm,@(R0,GBR) ICBI LDC Rm,DBR LDC Rm, SGR LDC Rm,SR LDC.L @Rm+,DBR LDC.L @Rm+,SGR [Legend] R: Rm/Rn @adr: Address SR1: MACH/MACL/PR SR2: FPUL/FPSCR CR1: GBR/Rp_BANK/SPC/SSR/VBR CR2: CR1/DBR/SGR FR: FRm/FRn/DRm/DRn/XDm/XDn The ...
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Section 4 Pipelining Table 4.3 Combination of Preceding and Following Instructions EX Following EX No Instruction MT Yes (addr+2) BR Yes LS Yes FE Yes CO No Note: The following table shows the parallel-executability of pairs of instructions in this ...
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Issue Rates and Execution Cycles Instruction execution cycles are summarized in table 4.4. Instruction Group in the table 4.4 corresponds to the category in the table 4.2. Penalty cycles due to a pipeline stall are not considered in the ...
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Section 4 Pipelining Table 4.4 Issue Rates and Execution Cycles Functional Category No. Instruction Data transfer 1 EXTS.B instructions 2 EXTS.W 3 EXTU.B 4 EXTU.W 5 MOV 6 MOV 7 MOVA 8 MOV.W 9 MOV.L 10 MOV.B 11 MOV.W 12 ...
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Functional Category No. Instruction Data transfer 30 MOV.L instructions 31 MOV.B 32 MOV.W 33 MOV.L 34 MOV.B 35 MOV.W 36 MOV.L 37 MOV.B 38 MOV.W 39 MOV.L 40 MOVCA.L 41 MOVCO.L 42 MOVLI.L 43 MOVUA.L 44 MOVUA.L 45 MOVT 46 ...
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Section 4 Pipelining Functional Category No. Instruction Fixed-point 61 CMP/HI arithmetic 62 CMP/HS instructions 63 CMP/PL 64 CMP/PZ 65 CMP/STR 66 DIV0S 67 DIV0U 68 DIV1 69 DMULS.L 70 DMULU MAC.L 73 MAC.W 74 MUL.L 75 MULS.W ...
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Functional Category No. Instruction Logical 92 TST.B instructions 93 XOR 94 XOR 95 XOR.B Shift 96 ROTL instructions 97 ROTR 98 ROTCL 99 ROTCR 100 SHAD 101 SHAL 102 SHAR 103 SHLD 104 SHLL 105 SHLL2 106 SHLL8 107 SHLL16 ...
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Section 4 Pipelining Functional Category No. Instruction System 123 NOP control 124 CLRMAC instructions 125 CLRS 126 CLRT 127 ICBI 128 SETS 129 SETT 130 PREFI 131 SYNCO 132 TRAPA 133 RTE 134 SLEEP 135 LDTLB 136 LDC 137 LDC ...
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Functional Category No. Instruction System 154 LDS control 155 LDS.L instructions 156 LDS.L 157 LDS.L 158 STC 159 STC 160 STC 161 STC 162 STC 163 STC 164 STC 165 STC 166 STC.L 167 STC.L 168 STC.L 169 STC.L 170 ...
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Section 4 Pipelining Functional Category No. Instruction Single- 185 FMOV.S precision 186 FMOV.S floating-point 187 FMOV.S instructions 188 FMOV.S 189 FLDS 190 FSTS 191 FABS 192 FADD 193 FCMP/EQ 194 FCMP/GT 195 FDIV 196 FLOAT 197 FMAC 198 FMUL 199 ...
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Functional Category No. Instruction Double- 216 FDIV precision 217 FLOAT floating-point 218 FMUL instructions 219 FNEG 220 FSQRT 221 FSUB 222 FTRC FPU system 223 LDS control 224 LDS instructions 225 LDS.L 226 LDS.L 227 STS 228 STS 229 STS.L ...
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Section 5 Exception Handling 5.1 Summary of Exception Handling Exception handling processing is handled by a special routine which is executed by a reset, general exception handling, or interrupt. For example, if the executing instruction ends abnormally, appropriate action must ...
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Section 5 Exception Handling 5.2.1 TRAPA Exception Register (TRA) The TRAPA exception register (TRA) consists of 8-bit immediate data (imm) for the TRAPA instruction. TRA is set automatically by hardware when a TRAPA instruction is executed. TRA can also be ...
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Exception Event Register (EXPEVT) The exception event register (EXPEVT) consists of a 12-bit exception code. The exception code set in EXPEVT is that for a reset or general exception event. The exception code is set automatically by hardware when ...
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Section 5 Exception Handling 5.2.3 Interrupt Event Register (INTEVT) The interrupt event register (INTEVT) consists of a 14-bit exception code. The exception code is set automatically by hardware when an exception occurs. INTEVT can also be modified by software. Bit: ...
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Exception Handling Functions 5.3.1 Exception Handling Flow In exception handling, the contents of the program counter (PC), status register (SR), and R15 are saved in the saved program counter (SPC), saved status register (SSR), and saved general register15 (SGR), ...
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Section 5 Exception Handling 5.4 Exception Types and Priorities Table 5.3 shows the types of exceptions, with their relative priorities, vector addresses, and exception/interrupt codes. Table 5.3 Exceptions Exception Execution Category Mode Exception Reset Abort type Power-on reset Manual reset ...
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Exception Execution Category Mode Exception General Completion Unconditional trap (TRAPA) exception type User break after instruction execution* Interrupt Completion Nonmaskable interrupt type General interrupt request Notes: 1. When UBDE in CBCR = DBR. In other cases, PC ...
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Section 5 Exception Handling 5.5 Exception Flow 5.5.1 Exception Flow Figure 5.1 shows an outline flowchart of the basic operations in instruction execution and exception handling. For the sake of clarity, the following description assumes that instructions are executed sequentially, ...
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Yes Reset requested? No Execute next instruction General Yes exception requested? No Yes Interrupt requested? SSR ← SPC ← PC SGR ← R15 EXPEVT/INTEVT ← exception code SR.{MD,RB,BL} ← 111 SR.IMASK ← received interuupt level (*) PC ← ...
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Section 5 Exception Handling 5.5.2 Exception Source Acceptance A priority ranking is provided for all exceptions for use in determining which of two or more simultaneously generated exceptions should be accepted. Five of the general exceptions—general illegal instruction exception, slot ...
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Exception Requests and BL Bit When the BL bit exceptions and interrupts are accepted. When the BL bit and an exception other than a user break is generated, the CPU's internal ...
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Section 5 Exception Handling 5.6 Description of Exceptions The various exception handling operations explained here are exception sources, transition address on the occurrence of exception, and processor operation when a transition is made. 5.6.1 Resets Power-On Reset: • Condition: Power-on ...
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Instruction TLB Multiple-Hit Exception: • Source: Multiple ITLB address matches • Transition address: H'A0000000 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is ...
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Section 5 Exception Handling 5.6.2 General Exceptions Data TLB Miss Exception: • Source: Address mismatch in UTLB address comparison • Transition address: VBR + H'00000400 • Transition operations: The virtual address (32 bits) at which this exception occurred is set ...
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Instruction TLB Miss Exception: • Source: Address mismatch in ITLB address comparison • Transition address: VBR + H'00000400 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page ...
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Section 5 Exception Handling Initial Page Write Exception: • Source: TLB is hit in a store access, but dirty bit • Transition address: VBR + H'00000100 • Transition operations: The virtual address (32 bits) at which this ...
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Data TLB Protection Violation Exception: • Source: The access does not accord with the UTLB protection information (PR bits) shown below. PR Privileged Mode 00 Only read access possible 01 Read/write access possible 10 Only read access possible 11 Read/write ...
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Section 5 Exception Handling Instruction TLB Protection Violation Exception: • Source: The access does not accord with the ITLB protection information (PR bits) shown below. PR Privileged Mode 0 Access possible 1 Access possible • Transition address: VBR + H'00000100 ...
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Data Address Error: • Sources: Word data access from other than a word boundary (2n +1) Longword data access from other than a longword data boundary (4n + +3) Quadword data access ...
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Section 5 Exception Handling Instruction Address Error: • Sources: Instruction fetch from other than a word boundary (2n +1) Instruction fetch from area H'80000000 to H'FFFFFFFF in user mode Area H'E5000000 to H'E5FFFFFF can be accessed in user ...
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Unconditional Trap: • Source: Execution of TRAPA instruction • Transition address: VBR + H'00000100 • Transition operations: As this is a processing-completion-type exception, the PC contents for the instruction following the TRAPA instruction are saved in SPC. The value of ...
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Section 5 Exception Handling General Illegal Instruction Exception: • Sources: Decoding of an undefined instruction not in a delay slot Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'FFFD Decoding in ...
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Slot Illegal Instruction Exception: • Sources: Decoding of an undefined instruction in a delay slot Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'FFFD Decoding of an instruction that modifies PC ...
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Section 5 Exception Handling General FPU Disable Exception: • Source: Decoding of an FPU instruction* not in a delay slot with SR.FD =1 • Transition address: VBR + H'00000100 • Transition operations: The PC and SR contents for the instruction ...
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Slot FPU Disable Exception: • Source: Decoding of an FPU instruction in a delay slot with SR.FD =1 • Transition address: VBR + H'00000100 • Transition operations: The PC contents for the preceding delayed branch instruction are saved in SPC. ...
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Section 5 Exception Handling Pre-Execution User Break/Post-Execution User Break: • Source: Fulfilling of a break condition set in the user break controller • Transition address: VBR + H'00000100, or DBR • Transition operations: In the case of a post-execution break, ...
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FPU Exception: • Source: Exception due to execution of a floating-point operation • Transition address: VBR + H'00000100 • Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR ...
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Section 5 Exception Handling 5.6.3 Interrupts NMI (Nonmaskable Interrupt): • Source: NMI pin edge detection • Transition address: VBR + H'00000600 • Transition operations: The PC and SR contents for the instruction immediately after this exception is accepted are saved ...
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General Interrupt Request: • Source: The interrupt mask level bits setting smaller than the interrupt level of interrupt request, and the BL bit (accepted at instruction boundary). • Transition address: VBR + H'00000600 ...
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Section 5 Exception Handling • Instructions that make two accesses to memory With MAC instructions, memory-to-memory arithmetic/logic instructions, TAS instructions, and MOVUA instructions, two data transfers are performed by a single instruction, and an exception will be detected for each ...
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Usage Notes 1. Return from exception handling A. Check the BL bit in SR with software. If SPC and SSR have been saved to memory, set the BL bit before restoring them. B. Issue an ...
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Section 5 Exception Handling 5. Changing the SR register value and accepting exception A. When the bit in the SR register is changed by the LDC instruction, the acceptance of the exception is determined by the changed ...
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Section 6 Floating-Point Unit (FPU) 6.1 Features The FPU has the following features. • Conforms to IEEE754 standard • 32 single-precision floating-point registers (can also be referenced as 16 double-precision registers) • Two rounding modes: Round to Nearest and Round ...
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Section 6 Floating-Point Unit (FPU) 6.2 Data Formats 6.2.1 Floating-Point Format A floating-point number consists of the following three fields: • Sign bit (s) • Exponent field (e) • Fraction field (f) The SH-4A can handle single-precision and double-precision floating-point ...
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Table 6.1 Floating-Point Number Formats and Parameters Parameter Single-Precision Total bit width 32 bits Sign bit 1 bit Exponent field 8 bits Fraction field 23 bits Precision 24 bits Bias +127 E +127 max E –126 min Floating-point number value ...
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Section 6 Floating-Point Unit (FPU) Table 6.2 Floating-Point Ranges Type Signaling non-number Quiet non-number Positive infinity Positive normalized number Positive denormalized number Positive zero Negative zero Negative denormalized number Negative normalized number Negative infinity Quiet non-number Signaling non-number Rev.1.00 Dec. ...
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Non-Numbers (NaN) Figure 6.3 shows the bit pattern of a non-number (NaN). A value is NaN in the following case: • Sign bit: Don't care • Exponent field: All bits are 1 • Fraction field: At least one bit ...
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Section 6 Floating-Point Unit (FPU) See SH-4A Software Manual for details of floating-point operations when a non-number (NaN) is input. 6.2.3 Denormalized Numbers For a denormalized number floating-point value, the exponent field is expressed as 0, and the fraction field ...
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Register Descriptions 6.3.1 Floating-Point Registers Figure 6.4 shows the floating-point register configuration. There are thirty-two 32-bit floating- point registers comprised with two banks: FPR0_BANK0 to FPR15_BANK0, and FPR0_BANK1 to FPR15_BANK1. These thirty-two registers are referenced as FR0 to FR15, ...
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Section 6 Floating-Point Unit (FPU) 7. Single-precision floating-point extended register matrix, XMTRX: XMTRX comprises all 16 XF registers. XMTRX = XF0 XF4 XF1 XF5 XF2 XF6 XF3 XF7 FPSCR. FV0 DR0 DR2 FV4 DR4 DR6 FV8 DR8 DR10 ...
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Floating-Point Status/Control Register (FPSCR) bit Initial value R/ bit Cause Initial value R/W: R/W R/W R/W R/W Bit Bit Name Initial Value 31 to ...
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Section 6 Floating-Point Unit (FPU) Bit Bit Name Initial Value Cause All Enable All Flag All 0 1 RM1 0 0 RM0 1 Rev.1.00 Dec. 13, 2005 Page 138 ...
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Floating-point register DR (2i (2i) FR (2i+ Memory area 8n 8n+3 8n+4 <Little endian> 63 Floating-point register DR (2i (2i) FR (2i+ Memory area 4n+3 4n 4m+3 ...
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Section 6 Floating-Point Unit (FPU) Table 6.3 Bit Allocation for FPU Exception Handling FPU Field Name Error (E) Cause FPU exception Bit 17 cause field Enable FPU exception None enable field Flag FPU exception None flag field 6.3.3 Floating-Point Communication ...
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Rounding In a floating-point instruction, rounding is performed when generating the final operation result from the intermediate result. Therefore, the result of combination instructions such as FMAC, FTRV, and FIPR will differ from the result when using a basic ...
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Section 6 Floating-Point Unit (FPU) 6.5 Floating-Point Exceptions 6.5.1 General FPU Disable Exceptions and Slot FPU Disable Exceptions FPU-related exceptions are occurred when an FPU instruction is executed with SR.FD set to 1. When the FPU instruction is in other ...
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Underflow (U): FPSCR.Enable and instruction with possibility of operation result underflow • Inexact exception (I): FPSCR.Enable and instruction with possibility of inexact operation result All exception events that originate in the FPU are assigned as ...
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Section 6 Floating-Point Unit (FPU) 6.6 Graphics Support Functions The SH-4A supports two kinds of graphics functions: new instructions for geometric operations, and pair single-precision transfer instructions that enable high-speed data transfer. 6.6.1 Geometric Operation Instructions Geometric operation instructions perform ...
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Matrix (4 × 4) × matrix (4 × 4): This operation requires the execution of four FTRV instructions. Since an inexact exception is not detected by an FIRV instruction, the inexact exception (I) bit in both the FPU exception ...
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Section 7 Memory Management Unit (MMU) This LSI supports an 8-bit address space identifier, a 32-bit virtual address space, and a 29-bit physical address space. Address translation from virtual addresses to physical addresses is enabled by the memory management unit ...
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Section 7 Memory Management Unit (MMU) When address translation from virtual memory to physical memory is performed using the MMU, it may happen that the translation information has not been recorded in the MMU, or the virtual memory of a ...