R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 911

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

23.3.4
SPTBR is a 32-bit readable/writable register that stores data to be transmitted.
Bit
2
1
0
Initial value:
Initial value:
Bit
31 to 8
7 to 0
R/W:
R/W:
Bit:
Bit:
Transmit Buffer Register (SPTBR)
Bit Name
RXDE
TXDE
MASL
Bit Name

TD
31
15
—
—
R
R
0
0
30
14
—
—
R
R
0
0
Initial
Value
All 0
All 0
29
13
—
—
R
R
0
0
Initial
Value
0
0
0
28
12
—
—
R
R
0
0
R/W
R/W
R/W
R/W
R/W
R
R/W
27
11
—
—
R
R
0
0
26
10
—
—
R
R
0
0
Description
Reserved
Although the initial value is 0, these bits will be read as
an undefined value. The write value should always be 0.
Transmit Data
Data written to this register is transferred to the shift
register for transmission.
When reading these bits, always read as data stored in
the transmit buffer.
Description
Receive DMA Enable
0: Receive DMA transfer request disabled
1: Receive DMA transfer request enabled
Transmit DMA Enable
0: Transmit DMA transfer request disabled
1: Transmit DMA transfer request enabled
Master/Slave Select Bit
0: HSPI module configured as a slave
1: HSPI module configured as a master
25
—
—
R
R
0
9
0
24
—
—
R
R
0
8
0
R/W
23
—
R
0
7
0
Section 23 Serial Protocol Interface (HSPI)
Rev.1.00 Dec. 13, 2005 Page 859 of 1286
R/W
22
—
R
0
6
0
R/W
21
—
R
0
5
0
R/W
20
—
R
0
4
0
TD
R/W
19
—
R
0
3
0
REJ09B0158-0100
R/W
18
—
R
0
2
0
R/W
17
—
R
0
1
0
R/W
16
—
R
0
0
0