R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 384
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 11 Local Bus State Controller (LBSC)
The MMSELR must be written by the CPU. Writing to MMSELR, the DMAC or PCIC module
must be set not to access to any resources, and all processing should be finished (for example, the
SYNCO instruction preceding the MOV instruction should be executed) before MMSELR is
modified.
In addition, execute the MOV instruction to read out MMSELR (a dummy read) twice and the
SYNCO instruction in succession immediately after a MOV instruction of write to MMSELR.
Example:
Rev.1.00 Dec. 13, 2005 Page 332 of 1286
REJ09B0158-0100
Bit
2 to 0
-----------------------------------------------------------------------
MOV.L
MOV.L
SYNCO
MOV.L
MOV.L
MOV.L
SYNCO
-----------------------------------------------------------------------
Bit Name
AREASEL
#H'FF400020, R0
#MMSELR_DATA, R1
R1, @R0
@R0, R2
@R0, R2
Initial
Value
000
R/W
R/W
Description
DDRIF/PCIC Memory Space Select
000: Sets area 3 (H'0C00 0000 to H'0FFF FFFF) as the DDRIF
001: Sets area 3 (H'0C00 0000 to H'0FFF FFFF) as the DDRIF
010: Sets areas 2 and 3 (H'0800 0000 to H'0FFF FFFF) as the
011: Sets areas 2 and 3 (H'0800 0000 to H'0FFF FFFF) as the
100: Sets areas 2 to 5 (H'0800 0000 to H'17FF FFFF) as the
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
;
; MMSELR_DATA=Writing value of MMSELR
;
; Writing to MMSELR
space and other areas as the LBSC space
space, area 4 (H'1000 0000 to H'13FF FFFF) as the PCI
memory space, and other areas as the LBSC space
DDRIF space and other areas as the LBSC space
DDRIF space, area 4 (H'1000 0000 to H'13FF FFFF) as
the PCI memory space, and other areas as the LBSC
space
DDRIF space
(upper word=H'A5A5)
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