R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 1078

IC SUPERH MPU ROMLESS 449-BGA

R8A77800ANBGAV

Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77800ANBGAV

Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 27 NAND Flash Memory Controller (FLCTL)
27.3.1
FLCMNCR is a 32-bit readable/writable register that specifies the type (NAND) of flash memory,
access mode, and FCE pin output.
Rev.1.00 Dec. 13, 2005 Page 1026 of 1286
REJ09B0158-0100
Bit
31 to 18
17
16
15
14
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Common Control Register (FLCMNCR)
Bit Name
QTSEL
FCKSEL
R/W
FCK
SEL
31
15
R
0
0
30
14
R
R
0
0
ECCPOS[1:0]
R/W
29
13
R
Initial
Value
All 0
0
0
0
0
0
0
R/W
28
12
R
0
0
R/W
27
11
R/W
R
R/W
R
R/W
R
R
0
0
ACM[1:0]
R/W
26
10
R
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Fourth-Divided Flash Clock Select
0: Uses the value in FCKSEL
1: Divides a peripheral clock (Pck) provided from the
Note: When FCKSEL = 1, setting to 1 to this bit is
Reserved
This bit is always read as 0. The write value should
always be 0.
Flash Clock Select
0: Divides a peripheral clock (Pck) provided from the
1: Uses a peripheral clock (Pck) provided from the CPG
Reserved
This bit is always read as 0. The write value should
always be 0.
NAND
R/W
25
WF
R
CPG by four and uses it as FCLK when FCKSEL = 0
CPG by two and uses it as FCLK
as FCLK
0
9
0
R/W
prohibited.
SE
24
R
0
8
0
23
R
R
0
7
0
22
R
R
0
6
0
21
R
R
0
5
0
20
R
R
0
4
0
R/W
CE0
19
R
0
3
0
18
R
R
0
2
0
QTSEL
R/W
17
R
0
1
0
R/W
TYPE
SEL
16
R
0
0
0

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