R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 308

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 10 Interrupt Controller (INTC)
Rev.1.00 Dec. 13, 2005 Page 256 of 1286
REJ09B0158-0100
Bit
25
24
23
Name
NMIB
NMIE
IRLM0
Initial
Value
0
0
0
R/W
R/W
R/W
R/W
Description
NMI Block Mode
Selects whether an NMI interrupt is held until the BL bit
in SR is cleared to 0 or detected immediately when the
BL bit in SR of the CPU is set to 1.
0: An NMI interrupt is held when the BL bit in SR is set
1: An NMI interrupt is not held when the BL bit in SR is
Note: If interrupts are accepted with the BL bit in SR
NMI Edge Select
Selects whether an interrupt request signal to the NMI
pin is detected at the rising edge or the falling edge.
0: An interrupt request is detected at the falling edge of
1: An interrupt request is detected at the rising edge of
Note: NMI interrupt is not detected for at least six bus
IRL Pin Mode 0
Selects whether IRQ/IRL3 to IRQ/IRL0 are used as 4-
bit level-encoded interrupt requests or as four
independent interrupts.
0: IRQ/IRL3 to IRQ/IRL0 are used as the 4-bit level-
1: IRQ/IRL3 to IRQ/IRL0 are used as four independent
Note: The level-encoded IRL interrupt is not detected
encoded interrupt requests (IRL [3:0] interrupt; initial
value)
interrupt requests (IRQ [n] interrupt; n = 3 to 0)
to 1 (initial value)
set to 1
NMI input (initial value)
NMI input
clock cycles after modification of this bit.
set to 1, information saved for any previous
exception (SSR, SPC, SGR, and INTEVT) is lost.
unless the same pin levels are sampled in four
consecutive bus clock cycles.