R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 867

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit
9
8
7, 6
Bit Name
RFFUL
RDREQ
—
Initial
Value
0
0
All 0
R/W
R
R
R
Description
Receive FIFO Full
0: Receive FIFO not full
1: Receive FIFO full
•
•
•
Receive Data Transfer Request
0: Indicates that the size of valid space in the receive
1: Indicates that the size of valid space in the receive
A receive data transfer request is issued when the valid
data space in the receive FIFO exceeds the size
specified by the RFWM bit in SIFCTR.
When using receive data transfer through the DMAC,
this bit is always cleared by one DMAC access. After
DMAC access, when conditions for setting this bit are
satisfied, the SIOF again indicates 1 for this bit.
•
•
•
Reserved
These bits are always read as 0. The write value should
always be 0.
FIFO does not exceed the size specified by the
RFWM bit in SIFCTR.
FIFO exceeds the size specified by the RFWM bit in
SIFCTR.
This bit is valid when the RXE bit in SICTR is 1.
This bit indicates a state; if SIRDR is read, the SIOF
clears this bit.
If the issue of interrupts by this bit is enabled, an
SIOF interrupt is issued.
This bit is valid when the RXE bit in SICTR is 1.
This bit indicates a state; if the size of valid data
space in the receive FIFO is less than the size
specified by the RFWM bit in SIFCTR, the SIOF
clears this bit.
If the issue of interrupts by this bit is enabled, an
SIOF interrupt is issued.
Rev.1.00 Dec. 13, 2005 Page 815 of 1286
Section 22 Serial I/O with FIFO (SIOF)
REJ09B0158-0100