R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 804

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 21 Serial Communication Interface with FIFO (SCIF)
Rev.1.00 Dec. 13, 2005 Page 752 of 1286
REJ09B0158-0100
Bit
7
6
Bit Name
ER
TEND
Initial
Value
0
1
R/W
R/W* Receive Error
R/W* Transmit End
Description
Indicates that a framing error or parity error occurred
during reception. The ER flag is not affected and
retains its previous state when the RE bit in SCSCR is
cleared to 0. When a receive error occurs, the receive
data is still transferred to SCFRDR, and reception
continues.
The FER and PER bits in SCFSR can be used to
determine whether there is a receive error in the
readout data from SCFRDR.
0: No framing error or parity error occurred during
[Clearing conditions]
•
•
1: A framing error or parity error occurred during
[Setting conditions]
•
•
Note: In 2-stop-bit mode, only the first stop bit is
Indicates that transmission has been ended without
valid data in SCFTDR after transmission of the last bit
of the transmit character.
0: Transmission is in progress
[Clearing conditions]
•
•
1: Transmission has been ended
[Setting conditions]
•
•
•
reception
reception
Power-on reset or manual reset
When 0 is written to ER after reading ER = 1
When the SCIF checks whether the stop bit at the
end of the receive data is 1 when reception ends,
and the stop bit is 0*
When, in reception, the number of 1-bits in the
receive data plus the parity bit does not match the
parity setting (even or odd) specified by the O/E bit
in SCSMR
When transmit data is written to SCFTDR, and 0 is
written to TEND after reading TEND = 1
When data is written to SCFTDR by the DMAC
Power-on reset or manual reset
When the TE bit in SCSCR is 0
When there is no transmit data in SCFTDR after
transmission of the last bit of a 1-byte serial
transmit character
checked for a value of 1; the second stop bit is
not checked.