R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 112

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 3 Instruction Set
Note:
Rev.1.00 Dec. 13, 2005 Page 60 of 1286
REJ09B0158-0100
Instruction
MOV.W
MOV.L
MOV.B
MOV.W
MOV.L
MOV.B
MOV.W
MOV.L
MOVA
MOVCO.L R0,@Rn
MOVLI.L
MOVUA.L @Rm,R0
MOVUA.L @Rm+,R0
MOVT
SWAP.B
SWAP.W Rm,Rn
XTRCT
*
Rm,Rn
@(R0,Rm),Rn
@(R0,Rm),Rn
R0,@(disp*,GBR)
R0,@(disp*,GBR)
R0,@(disp*,GBR)
@(disp*,GBR),R0
@(disp*,GBR),R0
@(disp*,GBR),R0
@(disp*,PC),R0 disp × 4 +
@Rm,R0
Rn
Rm,Rn
The assembler of Renesas uses the value after scaling (×1, ×2, or ×4) as the
displacement (disp).
Operation
(R0 + Rm) →
sign extension → Rn
(R0 + Rm) → Rn
R0 → (disp + GBR)
R0 → (disp × 2 + GBR)
R0 → (disp × 4 + GBR)
(disp + GBR) →
sign extension → R0
(disp × 2 + GBR) →
sign extension → R0
(disp × 4 + GBR) → R0
PC & H'FFFF FFFC
+ 4 → R0
LDST → T
If (T == 1) R0 → (Rn)
0 → LDST
1 → LDST
(Rm) → R0
When interrupt/exception
occurred 0 → LDST
(Rm) → R0
Load non-boundary alignment
data
(Rm) → R0, Rm + 4 → Rm
Load non-boundary alignment data
T → Rn
Rm → swap lower 2 bytes
→ Rn
Rm → swap upper/lower
words → Rn
Rm:Rn middle 32 bits → Rn
Instruction Code
0000nnnnmmmm1101 —
0000nnnnmmmm1110 —
11000000dddddddd —
11000001dddddddd —
11000010dddddddd —
11000100dddddddd —
11000101dddddddd —
11000110dddddddd —
11000111dddddddd —
0000nnnn01110011 
0000mmmm01100011 
0100mmmm10101001 
0100mmmm11101001 
0000nnnn00101001 —
0110nnnnmmmm1000 —
0110nnnnmmmm1001 —
0010nnnnmmmm1101 —
Privileged T Bit New
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LDST New
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New
New
New
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