R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 365

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

10.7.2
When switching between individual interrupt and level-encoded interrupt functions on the
IRQ/IRL[7:0] pins, the INTC may wind up holding an interrupt that was generated by mistake.
Therefore, to prevent the detection of such unintentional interrupts, mask all IRQ and IRL
interrupts before switching between IRQ/IRL[7:0] pin functions.
Table 10.14 Switching Sequence of IRQ/IRL[7:0] Pin Function
10.7.3
The procedure for clearing interrupts held in the INTC is as follows.
• To clear IRL interrupt requests
• To clear IRQ level-sense interrupt requests
Sequence item
1
2
3
4
When the holding function is in use (ICR0.LSH = 0), clear an IRL interrupt request from the
IRQ/IRL[3:0] pins by writing a 1 to the IM10 bit in INTMSK1, and clear an IRL interrupt
request from the IRQ/IRL[7:4] pins by writing a 1 to the IM11 bit in the same register. IRL
interrupt requests held in the detection circuit are not cleared even if each of the corresponding
interrupt levels is masked by the setting in INTMSK2.
When the holding function is not in use (ICR0.LSH = 1), interrupt requests are simply not
held.
When the holding function is in use (ICR0.LSH = 0), clear an IRQ level-sense interrupt
request from the IRQ/IRL[7:0] pins by writing a 1 to the corresponding mask bit (IM07 to
IM00) of INTMSK0.
Notes on Setting IRQ/IRL[7:0] Pin Function
To clear IRQ and IRL interrupt requests
IRL interrupt request and IRQ interrupt
request masking
Setting IRL/IRQ[7:4] pins to operate as
interrupt-request pins
Setting IRQ/IRL[7:0] pins for level-
encoded or individual interrupt request
input and setting usage of holding function
for IRQ level-sense or IRL interrupt
Start of IRL and IRQ interrupt detection
Procedure
Write 1 to all bits in INTMSK0 and
INTMSK1
Write 0 to the OMSEL12 bit in OMSELR
Write 0 to the PE6MD[1:0] bits in PECR
Set the IRLM[1:0] bits and the LSH bit in
ICR0
Write 1 to the corresponding bit in
INTMSKCLR0 and INTMSKCLR1
Rev.1.00 Dec. 13, 2005 Page 313 of 1286
Section 10 Interrupt Controller (INTC)
REJ09B0158-0100