R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 1167

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

29.2.5
CDR1 is a readable/writable 32-bit register which specifies the data value to be included in the
break conditions for channel 1.
Bit
31 to 0
Bit
31 to 0
Initial value :
Initial value :
R/W:
R/W:
Bit :
Bit :
Match Data Setting Register 1 (CDR1)
Bit Name
CAM
Bit Name
CD
R/W
R/W
31
15
R/W
R/W
30
14
Initial
Value
Undefined
R/W
R/W
Initial
Value
Undefined
29
13
R/W
R/W
28
12
R/W
R/W
27
11
R/W
R/W
R/W
R/W
R/W
R/W
26
10
Description
Compare Data Value
Specifies the data value to be included in the break
conditions.
When the operand bus has been specified using the
CBR1 register, specify the SDB data value in CD[31:0].
Description
Compare Address Mask
Specifies the bits to be masked among the address
bits which are specified using the CAR1 register. (Set
the bits to be masked to 1.)
0: Address bits CA[n] are included in the break
1: Address bits CA[n] are masked and not included in
[n] = any values from 31 to 0
R/W
R/W
25
9
condition.
the break condition.
R/W
R/W
24
8
CD
CD
R/W
R/W
23
7
Rev.1.00 Dec. 13, 2005 Page 1115 of 1286
R/W
R/W
22
6
Section 29 User Break Controller (UBC)
R/W
R/W
21
5
R/W
R/W
20
4
R/W
R/W
19
3
R/W
R/W
REJ09B0158-0100
18
2
R/W
R/W
17
1
R/W
R/W
16
0