R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 635

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Note:
Bit
1
0
*
Bit Name
NMIF
DME
Writing 0 is possible to clear the flag.
Initial
Value
0
0
R/W
R/(W)* NMI Flag
R/W
Descriptions
Indicates that an NMI interrupt occurred. If this bit is set,
DMA transfer is disabled even if the DE bit in CHCR
and the DME bit in DMAOR are set to 1.
When the NMI is input, the DMA transfer in progress
can be done in at least one transfer unit. When the
DMAC is not in operational, the NMIF bit is set to 1
even if the NMI interrupt was input.
0: No NMI interrupt
[Clearing condition]
Writing NMIF = 0 after NMIF = 1 read
1: NMI interrupt occurs
DMA Master Enable
Enables or disables DMA transfers on all channels 0 to
5 (DMAOR0) or 6 to 11 (DMAOR1). If the DME bit and
the DE bit in CHCR are set to 1, transfer is enabled. In
this time, all of the bits TE in CHCR, NMIF, and AE in
DMAOR must be 0. If this bit is cleared during transfer,
transfers in all channels 0 to 5 (DMAOR0) or 6 to 11
(DMAOR1) are terminated.
0: Disables DMA transfers on all channels
1: Enables DMA transfers on all channels
(Channels 0 to 5 by DMAOR0, 6 to 11 by DMAOR1)
(Channels 0 to 5 by DMAOR0, 6 to 11 by DMAOR1)
Section 14 Direct Memory Access Controller (DMAC)
Rev.1.00 Dec. 13, 2005 Page 583 of 1286
REJ09B0158-0100