R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 900

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 22 Serial I/O with FIFO (SIOF)
16-bit Stereo Data (4): Synchronous pulse method, falling edge sampling, slot No.0 used for left-
channel data, slot No.2 used for right-channel data, slot No.1 used for control data for channel 0 ,
slot No.3 used for control data for channel 1, and frame length = 128 bits
Synchronization-Pulse Output Mode at End of Each Slot (SYNCAT Bit = 1): Synchronous
pulse method, falling edge sampling, slot No.0 used for left-channel data, slot No.1 used for right-
channel data, slot No.2 used for control data for channel 0, slot No.3 used for control data for
channel 1, and frame length = 128 bits
In this mode, valid data must be set to slot No. 0.
Rev.1.00 Dec. 13, 2005 Page 848 of 1286
REJ09B0158-0100
SIOF_SYNC
SIOF_SYNC
SIOF_RXD
SIOF_SCK
SIOF_TXD
SIOF_SCK
SIOF_RXD
SIOF_TXD
Specifications:
Figure 22.19 Transmit and Receive Timing (16-Bit Stereo Data (4))
Specifications:
Figure 22.20 Transmit and Receive Timing (16-Bit Stereo Data)
Slot No.0
Slot No.0
L-channel
L-channel
data
data
1 bit delay
TRMD[1:0] = 00 or 10,
TDLE = 1,
RDLE = 1,
CD0E = 1,
TRMD[1:0] = 00 or 10,
TDLE = 1,
RDLE = 1,
CD0E = 1,
Slot No.1
channel 0
R-channel
Slot No.1
Control
data
Slot No.2
R-channel
channel 0
Slot No.2
Control
data
REDG = 0,
TDLA[3:0] = 0000,
RDLA[3:0] = 0000,
CD0A[3:0] = 0010,
REDG = 1,
TDLA[3:0] = 0000,
RDLA[3:0] = 0000,
CD0A[3:0] = 0001,
1 frame
Slot No.3
channel 1
Control
channel 1
Slot No.3
Control
1 frame
Slot No.4
FL[3:0] = 1110 (frame length: 128 bits),
TDRE = 1,
RDRE = 1,
CD1E = 1,
Slot No.4
FL[3:0] = 1110 (frame length: 128 bits)
TDRE = 1,
RDRE = 1,
CD1E = 1,
Slot No.5
Slot No.5
TDRA[3:0] = 0001,
RDRA[3:0] = 0001,
CD1A[3:0] = 0011
TDRA[3:0] = 0010,
RDRA[3:0] = 0010,
CD1A[3:0] = 0011
Slot No.6
Slot No.6
Slot No.7
Slot No.7