R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 534

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 13 PCI Controller (PCIC)
Rev.1.00 Dec. 13, 2005 Page 482 of 1286
REJ09B0158-0100
Bit
8
7
6
5, 4
3
2
Bit Name
TBS

BMAM

SERR
IOCS
Initial
Value
0
0
0
Undefined
0
0
R/W
SH: R/W
PCI: R
SH: R
PCI: R
SH: R/W
PCI: R
SH: R
PCI: R
SH: R/W
PCI: R
SH: R/W
PCI: R
Description
Byte Swap
Specifies whether or not byte data is swapped when
accessing to the PCI local bus.
0: No swap
1: Byte data is swapped
Reserved
These bits are always read as 0. The write value
should always be 0.
Bus Master Arbitration
Controls the PCI bus arbitration mode when the PCIC
operates in host bus bridge mode. This bit is ignored
when the PCIC operates in normal mode.
0: Fixed mode (PCIC > device0 > device1 > device2 >
1: Pseudo round robin (the most recently granted
Reserved
These bits are always read as an undefined value.
The write value should always be 0.
SERR Output
Controls the SERR output by software. This bit is valid
only in normal mode (do not use in host bus bridge
mode). This bit is valid only when the SERRE bit in
PCICMD is 1.
0: Makes SERR output high-impedance state (driven
1: Asserts SERR output during one PCICLK clock
INTA Output
Controls the INTA output by software. This bit is valid
only in normal mode.
0: Makes INTA output high-impedance state (driven
1: Asserts INTA output (low level output)
For details, see section 13.4.3 (5), Endian or
device is assigned the lowest priority)
device3)
high by pull-up register)
high by pull-up registor)
section 13.4.4 (6), Endian.
cycle (low level output)