R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 318
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 318 of 1342
- Download datasheet (7Mb)
Section 10 Interrupt Controller (INTC)
10.3.6
INTMSKCLR0 to INTMSKCLR2 are 32-bit write-only registers that clear the mask settings for
each interrupt request. Values read are undefined.
• Interrupt mask clear register 0 (INTMSKCLR0)
Rev.1.00 Dec. 13, 2005 Page 266 of 1286
REJ09B0158-0100
Initial value:
Initial value:
Bit
31
30
29
28
27
26
25
24
23 to 0
R/W:
R/W:
Bit:
Bit:
Interrupt Mask Clear Registers (INTMSKCLR0 to INTMSKCLR2)
Name
IC00
IC01
IC02
IC03
IC04
IC05
IC06
IC07
—
IC00 IC01
R/W
31
15
R
0
0
R/W
30
14
R
0
0
IC02
R/W
Initial
Value
0
0
0
0
0
0
0
0
All 0
29
13
R
0
0
IC03
R/W
28
12
R
0
0
IC04
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
27
11
R
0
0
IC05
R/W
26
10
R
0
0
Description
Clears masking of IRQ0 as
an individual pin interrupt
request.
Clears masking of IRQ1 as
an individual pin interrupt
request.
Clears masking of IRQ2 as
an individual pin interrupt
request.
Clears masking of IRQ3 as
an individual pin interrupt
request.
Clears masking of IRQ4 as
an individual pin interrupt
request.
Clears masking of IRQ5 as
an individual pin interrupt
request.
Clears masking of IRQ6 as
an individual pin interrupt
request.
Clears masking of IRQ7 as
an individual pin interrupt
request.
Reserved
These bits are always read as 0. The write value
should always be 0.
IC06
R/W
25
R
0
9
0
IC07
R/W
24
R
0
8
0
23
R
R
0
7
0
22
R
R
0
6
0
21
R
R
0
5
0
[When reading]
Values read are
undefined.
[When writing]
0: No effect
1: Clears the
20
R
R
0
4
0
corresponding interrupt
mask (enables the
interrupt)
19
R
R
0
3
0
18
R
R
0
2
0
17
R
R
0
1
0
16
R
R
0
0
0
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