R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 631

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit
2
1
Bit Name
IE
TE
Initial
Value
0
0
R/W
R/W
R/(W)* Transfer End Flag
Descriptions
Interrupt Enable
Specifies whether or not an interrupt request is
generated to the CPU at the end of the final DMA
transfer. Setting this bit to 1 generates an interrupt
request (DMINT) to the CPU when the TE bit is set to 1
and the final DMA transfer of read cycle ended. To
confirm the final end of the transfer, execute a dummy
read of the destination space and issue the SYNCO
instruction.
0: Interrupt request is disabled.
1: Interrupt request is enabled.
Shows that DMA transfer ends. The TE bit is set to 1
when TCR becomes to 0 (and the DMAC starts
executing the final DMA transfer).
The TE bit is not set to 1 in either of the following cases.
•
•
To clear the TE bit, the TE bit should be written to 0
after reading 1.
Even if the DE bit is set to 1 while this bit is set to 1,
transfer is not enabled.
0: During the DMA transfer or DMA transfer has been
[Clearing condition]
Writing 0 after TE = 1 read
1: TCR = 0 (During the final DMA transfer or the DMA
interrupted
transfer ends)
DMA transfer ends due to an NMI interrupt or DMA
address error before TCR is cleared to 0.
DMA transfer is ended by clearing the DE bit and
DME bit in DMAOR.
Section 14 Direct Memory Access Controller (DMAC)
Rev.1.00 Dec. 13, 2005 Page 579 of 1286
REJ09B0158-0100