R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 297

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

10.1.1
The basic flow of exception handling for interrupts is as follows.
In interrupt exception handling, the contents of the program counter (PC), status register (SR), and
R15 are saved in the saved program counter (SPC), saved status register (SSR), and saved general
register15 (SGR), and the CPU starts execution of the interrupt exception handling routine at the
corresponding vector address. An interrupt exception handling routine is a program written by the
user to handle a specific exception. The interrupt exception handling routine is terminated and
control returned to the original program by executing a return-from-exception instruction (RTE).
This instruction restores the contents of PC and SR and returns control to the normal processing
routine at the point at which the exception occurred. The contents of SGR are not written back to
R15 by the RTE instruction.
1. The contents of the PC, SR and R15 are saved in SPC, SSR and SGR, respectively.
2. The block (BL) bit in SR is set to 1.
3. The mode (MD) bit in SR is set to 1.
4. The register bank (RB) bit in SR is set to 1.
5. In a reset, the FPU disable (FD) bit in SR is cleared to 0.
6. The exception code is written to bits 13 to 0 of the interrupt event register (INTEVT).
7. Processing is made to jump to the start address of the interrupt exception handling routine,
8. The flow of processing branches to the address corresponding to the interrupt within the
vector base register (VBR) + H'600.
exception handler and processing to handle the interrupt starts up.
Interrupt Method
Rev.1.00 Dec. 13, 2005 Page 245 of 1286
Section 10 Interrupt Controller (INTC)
REJ09B0158-0100