R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 412

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 11 Local Bus State Controller (LBSC)
When the SRAM or burst ROM interface is used, a bus width of 8, 16, or 32 bits is selectable with
bits SZ in CS5BCR. When the MPX interface is used, a bus width of 32 bits should be selected
through bits SZ in CS5BCR. When the PCMCIA interface is used, select a bus width of 8 or 16
bits with SZ in CS5BCR. For details, see section 11.3.2, Memory Bus Width.
When area 5 is accessed, the CS5 signal is asserted.
In addition, the RD signal, which can be used as OE, and write control signals WE0 to WE3 are
asserted. While the PCMCIA interface is used, the CE1A and CE2A signals, the RD signal,
(which can be used as OE), the WE0, WE1, WE2, and WE3 signals, (which can be used as, REG,
WE, IORD, and IOWR, respectively) are asserted.
For the number of bus cycles, 0 to 25 wait cycles inserted by CS5WCR can be selected.
Any number of wait cycles can be inserted in each bus cycle through the external wait pin (RDY).
(When the insert number is 0, the RDY signal is ignored.)
The setup time and hold time (cycle number) of the address and CS5 signals to the read and write
strobe signals can be set within a range of 0 to 7 cycles by CS5WCR. The BS hold cycles can be
set within a range of 0 to 1 when the number for the read and write strobe setup wait is 1 or more.
For the PCMCIA interface, the setup time of addresses to the read/write strobe signals (CE1A and
CE2A) can be specified within a range from 0 to 15 cycles through bits TEDA/B2 to TEDA/B0
and TEDA/B to TEHA/B in CS5PCR. In addition, the number of wait cycles can be specified
within a range from 0 to 50 cycles through bits PCWA/B1 and PCWA/B0. The number of wait
cycles specified by CS5PCR is added to the value specified by IW3 to IW0 in CS5WCR or
PCIW3 to PCIW0 in CS5PCR.
When using area 5 for the DDR-SDRAM interface, set the AREASEL bit in MMSELR. Then the
CS5 signal is not asserted. When the DDR-SDRAM is used, see section 12, DDR-SDRAM
Interface (DDRIF).
(7)
Area 6
For area 6, physical address bits 28 to 26 are 110.
The interfaces that can be set for this area are the SRAM, MPX, burst ROM, and PCMCIA
interfaces.
When the SRAM or burst ROM is used, a bus width of 8, 16, or 32 bits is selectable with bits SZ
in CS6BCR. When the MPX interface is used, a bus width of 32 bits should be selected through
bits SZ in CS6BCR. When the PCMCIA interface is used, select a bus width of 8 or 16 bits with
SZ in CS6BCR. For details, see section 11.3.2, Memory Bus Width.
Rev.1.00 Dec. 13, 2005 Page 360 of 1286
REJ09B0158-0100