R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 791

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

21.2
Table 21.1 shows the SCIF pin configuration.
Table 21.1 Pin Configuration
Notes:
Pin Name
SCIF0_SCK
SCIF0_RXD
SCIF0_TXD
SCIF0_CTS
SCIF0_RTS
SCIF1_SCK
SCIF1_RXD
SCIF1_TXD
These pins are made to function as serial pins by performing SCIF operation settings with
the C/A bit in SCSMR, the TE, RE, CKE1, and CKE0 bits in SCSCR, and the MCE bit in
SCFCR. Break state transmission and detection can be set in SCSPTR of the SCIF.
Channel 0 pins are multiplexed with the PCIC, HSPI, FLCTL, GPIO and mode control
pins, and channel 1 pins are multiplexed with the MMCIF, GPIO and mode control pins.
Input/Output Pins
Function
Channel 0 serial clock pin
Channel 0 receive data pin
Channel 0 transmit data pin
Channel 0 modem control pin
Channel 0 modem control pin
Channel 1 serial clock pin
Channel 1 receive data pin
Channel 1 transmit data pin
Section 21 Serial Communication Interface with FIFO (SCIF)
I/O
I/O
Input
Output
I/O
I/O
I/O
Input
Output
Rev.1.00 Dec. 13, 2005 Page 739 of 1286
Description
Clock input/output
Receive data input
Transmit data output
Transmission enabled
Transmission request
Clock input/output
Receive data input
Transmit data output
REJ09B0158-0100