R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 196
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 6 Floating-Point Unit (FPU)
6.6
The SH-4A supports two kinds of graphics functions: new instructions for geometric operations,
and pair single-precision transfer instructions that enable high-speed data transfer.
6.6.1
Geometric operation instructions perform approximate-value computations. To enable high-speed
computation with a minimum of hardware, the SH-4A ignores comparatively small values in the
partial computation results of four multiplications. Consequently, the error shown below is
produced in the result of the computation:
Maximum error = MAX (individual multiplication result ×
The number of significant digits is 24 for a normalized number and 23 for a denormalized number
(number of leading zeros in the fractional part).
In a future version of the SH Series, the above error is guaranteed, but the same result between
different processor cores is not guaranteed.
FIPR FVm, FVn (m, n: 0, 4, 8, 12): This instruction is basically used for the following purposes:
• Inner product (m ≠ n):
• Sum of square of elements (m = n):
Since an inexact exception is not detected by an FIPR instruction, the inexact exception (I) bit in
both the FPU exception cause field and flag field are always set to 1 when an FIPR instruction is
executed. Therefore, if the I bit is set in the FPU exception enable field, FPU exception handling
will be executed.
FTRV XMTRX, FVn (n: 0, 4, 8, 12): This instruction is basically used for the following
purposes:
• Matrix (4 × 4) ⋅ vector (4):
Rev.1.00 Dec. 13, 2005 Page 144 of 1286
REJ09B0158-0100
This operation is generally used for surface/rear surface determination for polygon surfaces.
This operation is generally used to find the length of a vector.
This operation is generally used for viewpoint changes, angle changes, or movements called
vector transformations (4-dimensional). Since affine transformation processing for angle +
parallel movement basically requires a 4 × 4 matrix, the SH-4A supports 4-dimensional
operations.
Graphics Support Functions
Geometric Operation Instructions
2
–MIN (number of multiplier significant digits–1, number of multiplicand significant digits–1)
) + MAX (result value × 2
–23
, 2
–149
)
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