R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 272
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 272 of 1342
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Section 8 Caches
8.6.3
The OC address array is allocated to addresses H'F400 0000 to H'F4FF FFFF in the P4 area. An
address array access requires a 32-bit address field specification (when reading or writing) and a
32-bit data field specification. The way and entry to be accessed are specified in the address field,
and the write tag, U bit, and V bit are specified in the data field.
In the address field, bits [31:24] have the value H'F4 indicating the OC address array, and the way
is specified by bits [14:13] and the entry by bits [12:5]. The association bit (A bit) [3] in the
address field specifies whether or not association is performed when writing to the OC address
array. As only longword access is used, 0 should be specified for address field bits [1:0].
In the data field, the tag is indicated by bits [31:10], the U bit by bit [1], and the V bit by bit [0].
As the OC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a
write in which association is not performed. Data field bits [31:29] are used for the virtual address
specification only in the case of a write in which association is performed.
The following three kinds of operation can be used on the OC address array:
1. OC address array read
2. OC address array write (non-associative)
3. OC address array write (associative)
Rev.1.00 Dec. 13, 2005 Page 220 of 1286
REJ09B0158-0100
The tag, U bit, and V bit are read into the data field from the OC entry corresponding to the
way and entry set in the address field. In a read, associative operation is not performed
regardless of whether the association bit specified in the address field is 1 or 0.
The tag, U bit, and V bit specified in the data field are written to the OC entry corresponding to
the way and entry set in the address field. The A bit in the address field should be cleared to 0.
When a write is performed to a cache line for which the U bit and V bit are both 1, after write-
back of that cache line, the tag, U bit, and V bit specified in the data field are written.
When a write is performed with the A bit in the address field set to 1, the tag in each way
stored in the entry specified in the address field is compared with the tag specified in the data
field. The way numbers of bits [14:13] in the address field are not used. If the MMU is enabled
at this time, comparison is performed after the virtual address specified by data field bits
[31:10] has been translated to a physical address using the UTLB. If the addresses match and
the V bit in the way is 1, the U bit and V bit specified in the data field are written into the OC
entry. In other cases, no operation is performed. This operation is used to invalidate a specific
OC entry. If the OC entry U bit is 1, and 0 is written to the V bit or to the U bit, write-back is
performed. If a UTLB miss occurs during address translation, or the comparison shows a
mismatch, an exception is not generated, no operation is performed, and the write is not
executed.
OC Address Array
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