R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 1048

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 26 Serial Sound Interface (SSI) Module
Note:
Rev.1.00 Dec. 13, 2005 Page 996 of 1286
REJ09B0158-0100
Bit
1
0
*
These bits are readable/writable bits. If writing 0, these bits are initialized, although
writing 1 is ignored.
Bit Name
SWNO
IDST
1
1
Initial
Value
R/W
R
R
Description
Serial Word Number
The number indicates the current word number.
When TRMD = 0 (Receive Mode):
This bit indicates which system word the current data in
SSIRDR is. Regardless whether the data has been read
out from SSIRDR, when the data in SSIRDR is updated
by transfer from the shift register, this value will change.
When TRMD = 1 (Transmit Mode):
This bit indicates which system word should be written
in SSITDR. When data is copied to the shift register,
regardless whether the data is written in SSITDR, this
value will change.
Idle Mode Status Flag
Indicates that the serial bus activity has ceased.
This bit is cleared if EN = 1 and the Serial Bus is
currently active.
This bit can be set to 1 automatically under the
following conditions.
SSI = Serial bus master transmitter (SWSD = 1 and
TRMD = 1):
This bit is set to 1 if no more data has been written to
SSITDR and the current system word has been
completed. It can also be set to 1 by clearing the EN bit
after sufficient data has been written to SSITDR to
complete the system word currently being output.
SSI = Serial bus master receiver (SWSD = 1 and TRMD
= 0):
This bit is set to 1 if the EN bit is cleared and the current
system word is completed.
SSI = slave transmitter/ receiver (SWSD = 0):
This bit is set to 1 if the EN bit is cleared and the current
system word is completed.
Note: If the external device stops the serial bus clock
before the current system word is completed
then this bit will never be set.