R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 18

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 14 Direct Memory Access Controller (DMAC)................................... 557
14.1 Features.............................................................................................................................. 557
14.2 Input/Output Pins............................................................................................................... 559
14.3 Register Descriptions......................................................................................................... 561
14.4 Operation ........................................................................................................................... 588
14.5 Usage Notes ....................................................................................................................... 608
Rev.1.00 Dec. 13, 2005 Page xvi of l
13.4.4 Target Access........................................................................................................ 532
13.4.5 Host Bus Bridge Mode ......................................................................................... 541
13.4.6 Normal mode ........................................................................................................ 544
13.4.7 Power Management .............................................................................................. 544
13.4.8 PCI Local Bus Basic Interface.............................................................................. 545
14.3.1 DMA Source Address Registers 0 to 11 (SAR0 to SAR11) ................................. 567
14.3.2 DMA Source Address Registers B0 to B3, B6 to B9
14.3.3 DMA Destination Address Registers 0 to 11 (DAR0 to DAR11) ........................ 568
14.3.4 DMA Destination Address Registers B0 to B3, B6 to B9
14.3.5 DMA Transfer Count Registers 0 to 11 (TCR0 to TCR11).................................. 570
14.3.6 DMA Transfer Count Registers B0 to B3, B6 to B9
14.3.7 DMA Channel Control Registers 0 to 11 (CHCR0 to CHCR11) ......................... 572
14.3.8 DMA Operation Register 0, 1 (DMAOR0 and DMAOR1) .................................. 581
14.3.9 DMA Extended Resource Selectors (DMARS0 to DMARS2)............................. 584
14.4.1 DMA Transfer Requests ....................................................................................... 588
14.4.2 Channel Priority.................................................................................................... 592
14.4.3 DMA Transfer Types............................................................................................ 595
14.4.4 DMA Transfer Flow ............................................................................................. 602
14.4.5 Repeat Mode Transfer .......................................................................................... 604
14.4.6 Reload Mode Transfer .......................................................................................... 605
14.4.7 DREQ Pin Sampling Timing ................................................................................ 606
14.5.1 Module Stop ......................................................................................................... 608
14.5.2 Address Error........................................................................................................ 608
14.5.3 Notes on Burst Mode Transfer.............................................................................. 608
14.5.4 DACK output division .......................................................................................... 609
14.5.5 Clear DMINT Interrupt......................................................................................... 609
14.5.6 CS Output Settings and Transfer Size Larger than External Bus Width............... 609
14.5.7 DACK Assertion and DREQ Sampling ................................................................ 609
(SARB0 to SARB3, SARB6 to SARB9) .............................................................. 568
(DARB0 to DARB3, DARB6 to DARB9) ........................................................... 569
(TCRB0 to TCRB3, TCRB6 to TCRB9) .............................................................. 571