R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 103
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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This LSI's instruction set is implemented with 16-bit fixed-length instructions. This LSI can use
byte (8-bit), word (16-bit), longword (32-bit), and quadword (64-bit) data sizes for memory
access. Single-precision floating-point data (32 bits) can be moved to and from memory using
longword or quadword size. Double-precision floating-point data (64 bits) can be moved to and
from memory using longword size. When this LSI moves byte-size or word-size data from
memory to a register, the data is sign-extended.
3.1
PC: At the start of instruction execution, the PC indicates the address of the instruction itself.
Load-Store Architecture: This LSI has a load-store architecture in which operations are basically
executed using registers. Except for bit-manipulation operations such as logical AND that are
executed directly in memory, operands in an operation that requires memory access are loaded
into registers and the operation is executed between the registers.
Delayed Branches: Except for the two branch instructions BF and BT, this LSI's branch
instructions and RTE are delayed branches. In a delayed branch, the instruction following the
branch is executed before the branch destination instruction.
Delay Slot: This execution slot following a delayed branch is called a delay slot. For example, the
BRA execution sequence is as follows:
Table 3.1
A slot illegal instruction exception may occur when a specific instruction is executed in a delay
slot. For details, see section 5, Exception Handling. The instruction following BF/S or BT/S for
which the branch is not taken is also a delay slot instruction.
TARGET
Execution Environment
Execution Order of Delayed Branch Instructions
target-inst
BRA
ADD
:
:
Section 3 Instruction Set
TARGET
Instructions
(Delayed branch instruction)
(Delay slot)
(Branch destination instruction)
Rev.1.00 Dec. 13, 2005 Page 51 of 1286
Section 3 Instruction Set
BRA
↓
ADD
↓
target-inst
Execution Order
REJ09B0158-0100
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