R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 882

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 22 Serial I/O with FIFO (SIOF)
Transmit/Receive Timing: The SIOF_TXD transmit timing and SIOF_RXD receive timing
relative to the SIOF_SCK can be set as the sampling timing in the following two ways. The
transmit/receive timing is set using the REDG bit in SIMDR.
• Falling-edge sampling
• Rising-edge sampling
Figure 22.4 shows the transmit/receive timing.
22.4.3
The SIOF performs the following transfer.
• Transmit/receive data: Transfer of 8-bit data/16-bit data/16-bit stereo data
• Control data: Transfer of 16-bit data (uses the specific register as interface)
Transfer Mode: The SIOF supports the following four transfer modes as listed in table 22.6. The
transfer mode can be specified by the bits TRMD[1:0] in SIMDR.
Table 22.6 Serial Transfer Modes
Note:
Rev.1.00 Dec. 13, 2005 Page 830 of 1286
REJ09B0158-0100
SIOF_SCK
SIOF_RXD
SIOF_SYNC
SIOF_TXD
TRMD[1:0]
00
01
10
11
(a) Falling-edge sampling
*
Transfer Data Format
The control data method is valid only when the FL bits are specified as B'1xxx (x: don't
care).
Transfer Mode
Slave mode 1
Slave mode 2
Master mode 1
Master mode 2
Figure 22.4 SIOF Transmit/Receive Timing
REDG = 0
Receive timing
Transmit timing
SIOF_SYNC
Synchronous pulse
Synchronous pulse
Synchronous pulse
L/R
SIOF_SCK
SIOF_RXD
SIOF_SYNC
SIOF_TXD
(a) Rising-edge sampling
Bit Delay
SYNCDL bit
No
REDG = 1
Control Data*
Slot position
Secondary FS
Slot position
Not supported
Receive timing
Transmit timing