R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 1081

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Note:
Bit
23, 22
21
20
19, 18
17
16
15 to 0
*
Bit Name
—
SELRW
DOADR
ADRCNT
[1:0]
DOCMD2
DOCMD1
SCTCNT
[15:0]
Refer to figure 27.2 for command stage, address stage and data stage.
Initial
Value
All 0
0
0
00
0
0
H'0000
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Data Read/Write Specification
Specifies the direction of read or write in data stage.
0: Read
1: Write
Address Stage Execution Specification
Specifies whether or not the address stage is executed
in command access mode.
0: Performs no address stage
1: Performs address stage
Address Issue Byte Count Specification
Specify the number of bytes for the address data to be
issued in address stage*.
00: Issue 1-byte address
01: Issue 2-byte address
10: Issue 3-byte address
11: Issue 4-byte address
Second Command Stage Execution Specification
Specifies whether or not the second command stage* is
executed in command access mode.
0: Does not execute the second command stage
1: Executes the second command stage
First Command Stage Execution Specification
Specifies whether or not the first command stage* is
executed in command access mode.
0: Does not execute the first command stage
1: Executes the first command stage
Sector Transfer Count Specification
Specify the number of sectors to be read continuously
in sector access mode. These bits are counted down for
each sector transfer end and stop when they reach 0. In
command access mode, these bits become H'0001.
When accessing one sector, set H'0001 to the
SCTCNT.
Section 27 NAND Flash Memory Controller (FLCTL)
Rev.1.00 Dec. 13, 2005 Page 1029 of 1286
REJ09B0158-0100