R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 640

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 14 Direct Memory Access Controller (DMAC)
14.4
When there is a DMA transfer request, the DMAC starts the transfer according to the
predetermined channel priority; when the transfer end conditions are satisfied, it ends the transfer.
Transfers can be requested in three modes: auto request, external request, and peripheral module
request. In bus mode, burst mode or cycle steal mode can be selected.
14.4.1
DMA transfer requests are basically generated in either the data transfer source or destination, but
they can also be generated by external devices or peripheral modules that are neither the source
nor the destination. Transfers can be requested in three modes: auto request, external request, and
peripheral module request. The request mode is selected in the bits RS[3:0] in CHCR0 to
CHCR11 respectively, and DMARS0 to DMARS2 when peripheral module request is used.
Auto-Request Mode: When there is no transfer request signal from an external source, as in a
memory-to-memory transfer or a transfer between memory and an on-chip module unable to
request a transfer, auto-request mode allows the DMAC to automatically generate a transfer
request signal internally. Specify B'0100 to the RS [3:0] bits in CHCRn (n = 0 to 11) of the using
DMA channel. When the DE bit in CHCR for corresponding channel and the DME bit in
DMAOR0 for channels 0 to 5, DMAOR1 for channels 6 to11 are set to 1, the transfer begins so
long as the AE and NMIF bits in that DMAOR are all 0.
External Request Mode: In this mode, a transfer is performed at the request signal (DREQ) of an
external device. This mode is valid only in channel 0 to 3. Specify B'0000 to the RS [3:0] bits in
CHCRn (n = 0 to 3) of the using DMA channel. When this mode is selected, if the DMA transfer
is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0), a transfer is performed upon a request
at the DREQ input.
Choose to detect DREQ by either the edge or level of the signal input with the DL bit and DS bit
in CHCRn (n = 0 to 3) as shown in table 14.5. The source of the transfer request does not have to
be the data transfer source or destination.
Rev.1.00 Dec. 13, 2005 Page 588 of 1286
REJ09B0158-0100
Operation
DMA Transfer Requests