R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 216

IC SUPERH MPU ROMLESS 449-BGA

R8A77800ANBGAV

Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77800ANBGAV

Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 7 Memory Management Unit (MMU)
7.2.6
PASCR controls the operation in the physical address space.
Initial value:
Initial value:
Rev.1.00 Dec. 13, 2005 Page 164 of 1286
REJ09B0158-0100
Bit
31 to 8
7 to 0
R/W:
R/W:
Bit:
Bit:
Physical Address Space Control Register (PASCR)
31
15
Bit Name
UB
R
R
0
0
30
14
R
R
0
0
29
13
R
R
0
0
All 0
All 0
Initial
Value
28
12
R
R
0
0
27
11
R
R
0
0
R/W
R
R/W
26
10
R
R
0
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Buffered Write Control for Each Area (64 Mbytes)
When writing is performed without using the cache or
in the cache write-through mode, these bits specify
whether the next bus access from the CPU waits for
the end of writing for each area.
0: The CPU does not wait for the end of writing bus
1: The CPU waits for the end of writing bus access
UB[7]: Corresponding to the control register area
UB[6]: Corresponding to area 6
UB[5]: Corresponding to area 5
UB[4]: Corresponding to area 4
UB[3]: Corresponding to area 3
UB[2]: Corresponding to area 2
UB[1]: Corresponding to area 1
UB[0]: Corresponding to area 0
25
R
R
0
9
0
access and starts the next bus access
and starts the next bus access
24
R
R
0
8
0
R/W
23
R
0
7
0
R/W
22
R
0
6
0
R/W
21
R
0
5
0
R/W
20
R
0
4
0
UB
R/W
19
R
0
3
0
R/W
18
R
0
2
0
R/W
17
R
0
1
0
R/W
16
R
0
0
0

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