R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 1090

IC SUPERH MPU ROMLESS 449-BGA

R8A77800ANBGAV

Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77800ANBGAV

Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 27 NAND Flash Memory Controller (FLCTL)
Rev.1.00 Dec. 13, 2005 Page 1038 of 1286
REJ09B0158-0100
Bit
3
2
1
0
Bit Name
BTOINTE
TEINTE
TRINTE1
TRINTE0
0
Initial
Value
0
0
0
R/W
RW
R/W
R/W
R/W
Description
Interrupt Enable at Timeout Error
Enables or disables an interrupt request to the CPU
when a timeout error has occurred.
0: Disables the interrupt request to the CPU by a
1: Enables the interrupt request to the CPU by a
Transfer End Interrupt Enable
Enables or disables an interrupt request to the CPU
when a transfer has been ended (TREND bit in
FLTRCR).
0: Disables the transfer end interrupt request to the
1: Enables the transfer end interrupt request to the CPU
FLECFIFO Transfer Request Enable to CPU
Enables or disables an interrupt request to the CPU by
a transfer request issued from FLECFIFO.
0: Disables an interrupt request to the CPU by a
1: Enables an interrupt request to the CPU by a transfer
When the DMA transfer is enabled, this bit should be
cleared to 0.
FLDTFIFO Transfer Request Enable to CPU
Enables or disables an interrupt request to the CPU by
a transfer request issued from FLDTFIFO.
0: Disables an interrupt request to the CPU by a
1: Enables an interrupt request to the CPU by a transfer
When the DMA transfer is enabled, this bit should be
cleared to 0.
CPU
timeout error
timeout error
transfer request from FLECFIFO.
request from FLECFIFO.
transfer request from FLDTFIFO
request from FLDTFIFO

Related parts for R8A77800ANBGAV