R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 441

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

11.5.7
The byte control SRAM interface is a memory interface that outputs a byte-select strobe (WE) in
both read and write bus cycles. This interface has 16-bit data pins and can be connected to SRAM
having an upper byte select strobe and lower select strobe functions, such as UB and LB.
Areas 1 and 4 can be specified as a byte control SRAM interface. However, when these areas are
set to the MPX interface, the MPX interface has priority.
The write timing for the byte control SRAM interface is identical to that of a normal SRAM
interface.
In read operations, on the other hand, the WE pin timing is different. In a read access, only the WE
signal for the byte being read is asserted. Assertion is synchronized with the falling edge of the
CLKOUT clock in the same way as for the WE signal, while negation is synchronized with the
rising edge of the CLKOUT clock in the same way as for the RD signal.
In 32-byte transfer, a total of 32 bytes are transferred continuously according to the set bus width.
The first access is performed on the data for which there was an access request, and the remaining
accesses are performed in wraparound method according to the set bus width. The bus is not
released during this transfer.
Figure 11.30 shows an example of a byte control SRAM connection, and figures 11.31 to 11.33
show examples of byte-control SRAM read cycles.
Byte Control SRAM Interface
Figure 11.30 Example of 32-Bit Data-Width Byte-Control SRAM
SH7780
D31 to D16
D15 to D0
A17 to A2
WE3
WE2
WE1
WE0
CSn
R/W
RD
Section 11 Local Bus State Controller (LBSC)
Rev.1.00 Dec. 13, 2005 Page 389 of 1286
64 K × 16-bit
A15 to A0
CS
OE
WE
I/O15 to I/O0
UB
LB
A15 to A0
CS
OE
WE
I/O15 to I/O0
UB
LB
SRAM
REJ09B0158-0100