R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 479

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

V:
The DESELECT command in table 12.6 is automatically issued whenever the SDRAM is not
being accessed by any module. The DESELECT command therefore cannot be explicitly issued
by the user.
12.5.4
The DDRIF supports the following two SDRAM access modes. The BOMODE bits in MIM are
used to select the required mode.
Bank Open Mode: The SDRAM is accessed without the PRE command immediately after a
memory read or memory write, meaning that the bank is always open. This mode is useful for
applications in which a single bank is the target of consecutive memory accesses. When another
bank becomes the target, the PRE command is automatically issued.
Bank Closed Mode: Immediately after each round of reading or writing, the PRE command is
output and the target bank is closed. This mode is useful for applications in which the same bank
is unlikely to be the target of consecutive memory accesses.
12.5.5
(1)
The self-refresh mode is a standby state in which the SDRAM generates its own refresh timing
and refresh addresses. Once the self-refresh mode has been set by setting the DRE and RMODE
bits in MIM to 1, the self-refresh state is retained even if the CPU enters the sleep mode. If an
interrupt then takes the CPU out of the sleep mode, the self-refresh state is still retained.
Although the SDRAM is made to enter the self-refresh state by simply setting registers of the
DDRIF, the sequence given below should be followed.
Note that in the transition from auto-refresh state to self-refresh state, the current auto-refresh state
should have been finished or been disabled before the transition.
[Transition to self-refresh state]
1. Confirm that transactions to the DDRIF are completed.
2. Through software control, set the SMS bits in SCR to issue the PREALL (precharge all-banks)
command. This closes any SDRAM bank that was open. After that, use the SMS bits in SCR
to issue the REFA (auto-refresh) command to ensure that all memory rows are refreshed.
Self-Refresh Mode
Valid data
SDRAM Access Mode
Power-Down Modes
Section 12 DDR-SDRAM Interface (DDRIF)
Rev.1.00 Dec. 13, 2005 Page 427 of 1286
REJ09B0158-0100