R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 835
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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21.4.3
Clocked synchronous mode, in which data is transmitted or received in synchronization with clock
pulses, is suitable for fast serial communication.
Since the transmitter and receiver are independent units in the SCIF, full-duplex communication
can be achieved by sharing the clock. Both the transmitter and receiver have a 64-stage FIFO
buffer structure, so that data can be read or written during transmission or reception, enabling
continuous data transfer and reception.
Figure 21.15 shows the general format for clocked synchronous communication.
In clocked synchronous serial communication, data on the communication line is output from one
fall of the synchronization clock to the next fall. Data is guaranteed to be accurate at the start of
the synchronization clock.
In serial communication, each character is output starting with the LSB and ending with the MSB.
After the MSB is output, the communication line remains in the state of the last data.
In clocked synchronous mode, the SCIF receives data in synchronization with the rise of the
synchronization clock.
(1)
A fixed 8-bit data format is used. No parity bit can be added.
Data Transfer Format
Synchronization
clock
Serial data
Note: * High except in continuous transfer
Operation in Clocked Synchronous Mode
Figure 21.15 Data Format in Clocked Synchronous Communication
Don't care
*
LSB
Bit 0
Bit 1
One unit of transfer data (character or frame)
Section 21 Serial Communication Interface with FIFO (SCIF)
Bit 2
Bit 3
Bit 4
Rev.1.00 Dec. 13, 2005 Page 783 of 1286
Bit 5
Bit 6
Bit 7
MSB
Don't care
REJ09B0158-0100
*
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