R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 1012

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 25 Audio Codec Interface (HAC)
25.3.2
HACCSAR is a 32-bit read/write register that specifies the address of the codec register to be read
/written. When requesting a write to/read from a codec register, write the command register
address to HACCSAR. Then the HAC transmits this register address to the codec via slot 1.
read out from HACCSAR.
Rev.1.00 Dec. 13, 2005 Page 960 of 1286
REJ09B0158-0100
Initial value:
Initial value:
Bit
31 to 20
19
After the codec has responded to a read request (HACRSR.STARY = 1), the status address received via slot 1 can be
R/W:
R/W:
Bit:
Bit:
Command/Status Address Register (HACCSAR)
Bit Name

RW
CA3/
SA3
R/W
31
15

R
0
0
CA2/
SA2
R/W

30
14
R
0
0
CA1/
SA1
R/W
29
13

R
0
0
Initial
Value
All 0
0
CA0/
R/W
SA0
28
12

R
0
0
SLR
EQ3
R/W
R
R/W
27
11

R
R
0
0
SLR
EQ4
26

10
R
R
0
0
Description
Reserved
Always 0 for read and write.
Codec Read/Write Command
0: Notifies the off-chip codec device of a write access to
1: Notifies the off-chip codec device of a read access to
EQ5
SLR
the register specified in the address field (CA6/SA6 to
CA0/SA0).
Write the data to HACCSDR in advance.
When HACACR.TX12_ATOMIC is 1, the HAC
transmits HACCSAR and HACCSDR as a pair in the
same Tx frame.
When HACACR.TX12_ATOMIC is 0, transmission of
HACCSAR and HACCSDR in the same Tx frame is
not guaranteed.
the register specified in the address field (CA6/SA6 to
CA0/SA0).

25
R
R
0
9
0
EQ6
SLR
24

R
R
0
8
0
EQ7
SLR
23

R
R
0
7
0
SLR
EQ8
22

R
R
0
6
0
SLR
EQ9
21

R
R
0
5
0
EQ10
SLR
20

R
R
0
4
0
EQ11
R/W
RW
SLR
19
R
0
0
3
EQ12
CA6/
R/W
SA6
SLR
18
R
0
2
0
CA5/
SA5
R/W

17
R
0
1
0
CA4/
SA4
R/W
16

R
0
0
0