R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 1177

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

• When the Match Condition is Satisfied at the Instruction Fetch Cycle for Both the First and
• When the match condition is satisfied at the instruction fetch cycle for the first channel in the
• When the match condition is satisfied at the operand access cycle for the first channel in the
• When the match condition is satisfied at the operand access cycle for both the first and second
Instruction B is 0 instruction after instruction A
Instruction B is one instruction after instruction A Sequential operation is not guaranteed.
Instruction B is two or more instructions after
instruction A
Instruction B is 0 or one instruction after
instruction A
Instruction B is two or more instructions after
instruction A
Instruction B is 0 to five instructions after
instruction A
Instruction B is six or more instructions after
instruction A
Instruction B is 0 to five instructions after
instruction A
Instruction B is six or more instructions after
instruction A
Second Channels in the Sequence:
sequence whereas the match condition is satisfied at the operand access cycle for the second
channel in the sequence:
sequence whereas the match condition is satisfied at the instruction fetch cycle for the second
channel in the sequence:
channels in the sequence:
Equivalent to setting the same addresses; do
not use this setting.
Sequential operation is guaranteed.
Sequential operation is not guaranteed.
Sequential operation is guaranteed.
Sequential operation is not guaranteed.
Sequential operation is guaranteed.
Sequential operation is not guaranteed.
Sequential operation is guaranteed.
Rev.1.00 Dec. 13, 2005 Page 1125 of 1286
Section 29 User Break Controller (UBC)
REJ09B0158-0100