R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 861

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

22.3.4
SITDR is a 32-bit write-only register that specifies the SIOF operating status.
Initial value:
Initial value:
Bit
31 to 16 SITDL[15:0]
15 to 0
R/W:
R/W:
Bit:
Bit:
Transmit Data Register (SITDR)
Bit Name
SITDR[15:0]
31
15
—
—
W
W
30
14
—
W
—
W
29
13
—
W
—
W
Initial
Value
Undefined
Undefined
28
12
—
W
—
W
27
11
—
W
—
W
R/W
W
W
26
10
—
W
—
W
Description
Left-Channel Transmit Data
Specify data to be output from the SIOF_TXD pin as
left-channel data. The position of the left-channel data
in the transmit frame is specified by the TDLA bit in
SITDAR.
•
Right-Channel Transmit Data
Specify data to be output from the SIOF_TXD pin as
right-channel data. The position of the right-channel
data in the transmit frame is specified by the TDRA bit
in SITDAR.
•
25
—
—
W
W
9
These bits are valid only when the TDLE bit in
SITDAR is set to 1.
These bits are valid only when the TDRE bit and
TLREP bit in SITDAR are set to 1 and cleared to 0,
respectively.
SITDR[15:0]
SITDL[15:0]
24
—
—
W
W
8
23
—
—
W
W
7
Rev.1.00 Dec. 13, 2005 Page 809 of 1286
22
—
—
W
W
6
Section 22 Serial I/O with FIFO (SIOF)
21
—
W
—
W
5
20
—
W
—
W
4
19
—
W
—
W
3
REJ09B0158-0100
18
—
W
—
W
2
17
—
—
W
W
1
16
—
—
W
W
0