R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 890

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 22 Serial I/O with FIFO (SIOF)
22.4.7
Transmission in Master Mode: Figure 22.9 shows an example of settings and operation for
master mode transmission.
Rev.1.00 Dec. 13, 2005 Page 838 of 1286
REJ09B0158-0100
Note: * When interrupts due to transmit data underflow are enabled, after setting the no. 6 transmit data, the
No.
1
2
3
4
5
6
7
8
TXE bit should be set to 1.
Transmit and Receive Procedures
Transmit SITDR from SIOF_TXD
synchronously with SIOF_SYNC
Set the SCKE bit in SICTR to 1
Clear the TXE bit in SICTR to 0
SICDAR, SITCR, and SIFCTR
Set SIMDR, SISCR, SITDAR,
Set the FSE and TXE bits
Start SIOF_SCK output
Figure 22.9 Example of Transmit Operation in Master Mode
in SICTR to 1
TDREQ = 1?
Flow Chart
Set SITDR
Transfer
ended?
Start
End
Yes
Yes
No
No
Set to disable transmission
Set operating mode, serial clock,
slot positions for transmit data,
slot position for control data,
control data, and FIFO request
threshold value
Set the start for frame synchronous
signal output and enable
transmission
Set transmit data
Set operation start for baud rate
generator
SIOF Settings
Output serial clock
Output frame synchronous
signal and issue transmit
transfer request*
Transmit
End transmission
SIOF Operation