R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 466

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 12 DDR-SDRAM Interface (DDRIF)
Rev.1.00 Dec. 13, 2005 Page 414 of 1286
REJ09B0158-0100
Bit
28 to 16 DRI
15 to 12 LOCK
11, 10
9
Bit Name

DRE
Initial
Value
H'0C34
Undefined R
All 0
0
R/W
R
R/W
R/W
Description
DRAM Refresh Interval
When refreshing is valid (the DRE bit in MIM is set to
1), these bits specify the maximum refresh interval
(auto-refresh). The unit for counting is the cycle of the
MCLK. In 160-MHz operation, the unit corresponds to
6.3 ns. The smallest possible setting is H'0020 units. If
a lower setting is made, H'020 is added to the value for
counting.
The DDRIF has a 13-bit internal counter. When the
DCE or DRE bit is cleared to 0, or the RMODE bit is
set to 1, this counter is cleared to 0. Otherwise, the
counter is incremented by the external MCLK. The
value in the counter is compared with the DRI bits. If
the values match, an auto-refresh request is generated
in the controller and auto-refreshing is performed. Note
that the counter is cleared to 0 on the match, after
which incrementation begins again.
A single instance of the internally generated request for
auto-refresh is recorded; if the DCE and DRE bits are
set to 1 and the RMODE bit is cleared to 0, the auto-
refresh request is not cleared until auto-refreshing has
been performed. When setting these bits, start by
making the setting and writing a 0 to the DRE bit at the
same time. Make the setting again, but this time write a
1 to the DRE bit at the same time. This is required for
timing consistency.
DLL Lock Status
These bits indicate the state of locking by the DLL that
generates the read timing for the DDR-SDRAM When
these bits are all set to 1 and the DLLEN bit is 1,
access to memory is possible.
Reserved
These bits are always read as 0. The write value
should always be 0.
DRAM Refresh Enable
This bit enables or disables the use of refresh modes.
0: Disable
1: Enable