R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 841

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

In serial reception, the SCIF operates as described below.
1. The SCIF is initialized internally in synchronization with the input or output of the
2. The received data is stored in SCRSR in LSB-to-MSB order.
3. If the RIE bit in SCSCR is set to 1 when the RDF flag changes to 1, a receive-FIFO-data-full
Figure 21.20 shows an example of the operation for reception in clocked synchronous mode.
synchronization clock.
After receiving the data, the SCIF checks whether the receive data can be transferred from
SCRSR to SCFRDR. If this check is passed, the receive data is stored in SCFRDR. If an
overrun error is detected in the error check, reception cannot continue.
interrupt (RXI) request is generated.
If the RIE bit in SCSCR is set to 1 when the ORER flag changes to 1, a break interrupt (BRI)
request is generated.
Figure 21.19 Sample Serial Reception Flowchart (2)
No
Clear ORER flag in SCLSR to 0
Overrun error handling
Section 21 Serial Communication Interface with FIFO (SCIF)
Error handling
ORER = 1?
End
Yes
Rev.1.00 Dec. 13, 2005 Page 789 of 1286
REJ09B0158-0100