R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 930
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 930 of 1342
- Download datasheet (7Mb)
Section 24 Multimedia Card Interface (MMCIF)
• INTCR1
Rev.1.00 Dec. 13, 2005 Page 878 of 1286
REJ09B0158-0100
Bit
2
1
0
Bit
7
6
5
4, 3
Bit Name
CMDIE
DBSYIE
BTIE
Bit Name
INTRQ2E
INTRQ1E
INTRQ0E
—
Initial value:
Initial
Value
0
0
0
Initial
Value
0
0
0
All 0
R/W:
Bit:
INTR
Q2E
R/W
0
7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
INTR
Q1E
R/W
6
0
Description
Command Transmit End Interrupt Flag Setting Enable
0: Disables command transmit end interrupt (disables
1: Enables command transmit end interrupt (enables
Data Busy End Interrupt Flag Setting Enable
0: Disables data busy end interrupt (disables DBSYI
1: Enables data busy end interrupt (enables DBSYI flag
Multiple block Transfer End Flag Flag Setting Enable
0: Disables multiple block transfer end flag setting
1: Enables multiple block transfer end flag setting
Description
ERR Interrupt Enable
0: Disables ERR interrupt.
1: Enables ERR interrupt.
TRAN Interrupt Enable
0: Disables TRAN interrupt.
1: Enables TRAN interrupt.
FSTAT Interrupt Enable
0: Disables FSTAT interrupt.
1: Enables FSTAT interrupt.
Reserved
These bits are always read as 0. The write value should
always be 0.
INTR
Q0E
R/W
5
0
CMDI flag setting).
CMDI flag setting).
flag setting).
setting).
4
0
R
R
3
0
CRCE
RIE
R/W
2
0
R/W
DTE
RIE
1
0
R/W
CTE
RIE
0
0
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