R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 939
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R4F24278NVFQU
Manufacturer Part Number
R4F24278NVFQU
Description
MCU 512K/48K 2.7-5.5V 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet
1.R4F24278NVFQU.pdf
(1482 pages)
Specifications of R4F24278NVFQU
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R4F24278NVFQU
Manufacturer:
REALTEK
Quantity:
2 300
Company:
Part Number:
R4F24278NVFQU
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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H8S/2427, H8S/2427R, H8S/2425 Group
Note:
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Bit
3
2
1
0
Bit Name
STOP
MP
CKS1
CKS0
*
Can be written to only when TE = RE = 0.
Initial Value
0
0
0
0
R/W
R/W*
R/W*
R/W*
R/W*
Description
Stop Bit Length (enabled only in asynchronous
mode)
Selects the stop bit length in transmission.
0: 1 stop bit
1: 2 stop bits
In reception, only the first stop bit is checked
regardless of the STOP bit setting. If the second
stop bit is 0, it is treated as the start bit of the next
transmit character.
Multiprocessor Mode (enabled only in
asynchronous mode)
When this bit is set to 1, the multiprocessor
communication function is enabled. The PE bit
and O/E bit settings are invalid in multiprocessor
mode.
Clock Select 1 and 0
These bits select the clock source for the on-chip
baud rate generator.
00: φ clock (n = 0)
01: φ/4 clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
For the relation between the bit rate register
setting and the baud rate, see section 16.3.9, Bit
Rate Register (BRR). n is the decimal display of
the value of n in BRR (see section 16.3.9, Bit Rate
Register (BRR)).
Section 16 Serial Communication Interface (SCI, IrDA, CRC)
Page 909 of 1448
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