R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 1039

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
17.3.6
SAR is an 8-bit readable/writable register that sets slave address. When the chip is in slave mode,
if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition,
the chip operates as the slave device.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Bit
1
0
Bit
7 to 1
0
Bit Name
AAS
ADZ
Slave Address Register (SAR)
Bit Name
SVA6 to
SVA0
⎯
Initial Value
0
0
Initial Value
All 0
0
R/W
R/W
R/W
R/W
R/W
R/W
Description
Slave Address Recognition Flag
In slave receive mode, this flag is set to 1 if the first
frame following a start condition matches bits SVA6
to SVA0 in SAR.
[Setting condition]
•
•
[Clearing condition]
•
General Call Address Recognition Flag
This bit is valid in slave receive mode.
[Setting condition]
•
[Clearing conditions]
•
Description
Slave Address 6 to 0
These bits set a unique address in bits SVA6 to
SVA0, differing from the addresses of other slave
devices connected to the I
Reserved
This bit is readable/writable. The write value
should always be 0.
When the slave address is detected in slave
receive mode.
When the general call address is detected in
slave receive mode.
When 0 is written in AAS after reading AAS=1
When the general call address is detected in
slave receive mode.
When 0 is written in ADZ after reading ADZ=1.
Section 17 I
2
C bus.
2
C Bus Interface 2 (IIC2)
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