R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 218

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 7 Bus Controller (BSC)
7.3.11
REFCR specifies DRAM/synchronous DRAM interface refresh control.
Note: The synchronous DRAM interface is not supported by the H8S/2427 Group and H8S/2425
Page 188 of 1448
Bit
15
14
13
12
Group. The DRAM interface is not supported by the 5-V version.
Bit Name
CMF
CMIE
RCW1
RCW0
Refresh Control Register (REFCR)
0
0
0
0
Initial Value
R/W
R/(W)*
R/W
R/W
R/W
Description
Compare Match Flag
Status flag that indicates a match between the
values of RTCNT and RTCOR.
[Clearing conditions]
•
•
[Setting condition]
When RTCOR = RTCNT
Compare Match Interrupt Enable
Enables or disables interrupt requests (CMI) by
the CMF flag when the CMF flag is set to 1.
This bit is valid when refresh control is not
performed. When the refresh control is performed,
this bit is always cleared to 0 and cannot be
modified.
0: Interrupt request by CMF flag disabled
1: Interrupt request by CMF flag enabled
CAS-RAS Wait Control
These bits select the number of wait cycles to be
inserted between the CAS assert cycle and RAS
assert cycle in a DRAM/synchronous DRAM
refresh cycle.
00: Wait state not inserted
01: 1 wait state inserted
10: 2 wait states inserted
11: 3 wait states inserted
When 0 is written to CMF after reading CMF =
1 while the RFSHE bit is cleared to 0
When CBR refreshing is executed while the
RFSHE bit is set to 1
H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010