R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 875

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
• NDRLH*
• NDRLL*
Note: * When pulse output groups 2 and 3 have the same output trigger by PCR settings, the
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Bit
7
6
5
4
3 to 0
Bit
7 to 4
3
2
1
0
If pulse output groups 0 and 1 have different output triggers, upper 4 bits and lower 4 bits are
mapped to the different addresses as shown below.
Bit Name
⎯
NDR3
NDR2
NDR1
NDR0
Bit Name
NDR7
NDR6
NDR5
NDR4
⎯
NDRH address is H'FF4C. When they have different output triggers, the NDRH
addresses corresponding to the groups 2 and 3 are NDRHL (H'FF4E) and NDRHH
(H'FF4C), respectively. Also, when pulse output groups 0 and 1 have the same output
trigger by PCR settings, the NDRL address is H'FF4D. When they have different
output triggers, the NDRL addresses corresponding to the groups 0 and 1 are NDRLL
(H'FF4F) and NDRLH (H'FF4D), respectively.
Initial Value
0
0
0
0
All 1
Initial Value
All 1
0
0
0
0
R/W
R/W
R/W
R/W
R/W
⎯
R/W
⎯
R/W
R/W
R/W
R/W
Description
Next Data Register 7 to 4
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.
Reserved
These bits are always read as 1 and cannot be
modified.
Description
Reserved
These bits are always read as 1 and cannot be
modified.
Next Data Register 3 to 0
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.
Section 13 Programmable Pulse Generator (PPG)
Page 845 of 1448