R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 740

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R4F24278NVFQU

Manufacturer Part Number
R4F24278NVFQU
Description
MCU 512K/48K 2.7-5.5V 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet

Specifications of R4F24278NVFQU

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Section 11 I/O Ports
11.15.4 Port G Open Drain Control Register (PGODR)
PGODR specifies the output type of each port G pin.
Notes: 1. Not supported in the H8S/2427 and 2425 Groups.
Page 710 of 1448
Bit
7
6
5
4
3
2
1
0
Bit Name
PG6ODR
PG5ODR
PG4ODR
PG3ODR
PG2ODR
PG1ODR
PG0ODR
2. Not supported in the H8S/2427 and 2427R Groups.
3 Not supported in the 5-V version.
Initial Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
This bit is always read as 0. Only the initial value
should be written to this bit.
When not specified for BACK-A, BREQO-A, CS0,
CS1, CS2, CS3, CS4*
or CAS*
the corresponding pin an NMOS open-drain output
pin, while clearing a PGODR bit to 0 makes the
corresponding pin a CMOS output pin.
1
output, setting a PGODR bit to 1 makes
H8S/2427, H8S/2427R, H8S/2425 Group
2
, RAS2*
REJ09B0565-0100 Rev. 1.00
3
, RAS3*
3
, RAS*
Jul 22, 2010
1
,

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