R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 33

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Type
CPU
Interrupts
(sources)
Module/
Function
MCU
operating
mode
Interrupt
controller
Description
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Mode 1:
Mode 2:
Mode 3:
Mode 4:
Mode 5:
Mode 7:
Power-down modes (a power-down mode is entered when the
SLEEP instruction is executed)
External interrupt pins
H8S/2427 Group, H8S/2427R Group:
H8S/2425 Group:
Internal interrupt sources
H8S/2427 Group, H8S/2427R Group: 102 sources
H8S/2425 Group: 100 sources
Two interrupt control modes (specified by the interrupt control
register)
Eight priority levels can be set (specified by the interrupt priority
registers)
Independent vector addresses
33 pins (NMI, IRQ15-A to IRQ0-A, IRQ15-B to IRQ0-B)
17 pins (NMI, IRQ7-A to IRQ0-A, IRQ7-B to IRQ0-B)
Expanded mode with on-chip ROM disabled,
16-bit bus (MD2 and MD1 pins are low and MD0
pin is high)
Expanded mode with on-chip ROM disabled,
8-bit bus (MD2 pin is low, MD1 pin is high, and
MD0 pin is low)
Boot mode (MD2 pin is low and MD1 and MD0 pins
are high)
Expanded mode with on-chip ROM enabled,
8-bit bus (MD2 pin is high and MD1 and MD0 pins
are low)
User boot mode (MD2 pin is high, MD1 pin is low,
and MD0 pin is high)
Single-chip mode (MD2, MD1, and MD0 pins are
high)
Section 1 Overview
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