R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 721

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
11.14.1 Port F Data Direction Register (PFDDR)
The individual bits of PFDDR specify input or output for the pins of port F. PFDDR cannot be
read; if it is, an undefined value will be read.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Bit
7
6
5
4
3
2
1
0
Bit Name
PF7DDR
PF6DDR
PF5DDR
PF4DDR
PF3DDR
PF2DDR
PF1DDR
PF0DDR
Initial Value
1/0*
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
Description
•
Modes 1, 2, 4, and 3, 5, 7 (EXPE = 1)
Pin PF7 functions as the φ output pin when the
corresponding PFDDR bit is set to 1, and as an
input port when the bit is cleared to 0.
Pin PF6 functions as the AS output pin when the
ASOE bit is set to 1. When the ASOE bit is
cleared to 0, pin PF6 is an I/O port and its
function can be switched with PF6DDR.
Pins PF5 and PF4 are automatically designated
as bus control outputs (RD and HWR).
Pin PF3 functions as the LWR output pin when
the LWROE bit is set to 1. When the LWROE bit
is cleared to 0, pin PF3 is an I/O port and its
function can be switched with PF3DDR.
Pins PF2 and PF1 function as bus control output
pins (LCAS and UCAS) when the appropriate
bus controller settings are made. Otherwise,
operations differ between the H8S/2427 and
H8S/2427R Groups and H8S/2425 Group.
[H8S/2427 Group and H8S/2427R Group]
When pins PF2 and PF1 are general I/O ports,
the function can be switched with PFDDR.
[H8S/2425 Group]
Pins PF2 and PF1 function as CS output pins
when the CS output enable bits (CS6E and
CS5E) are set to 1, and as input ports when the
bits are cleared to 0. When the CS output
enable bits (CS6E and CS5E) are cleared to 0
and pins PF2 and PF1 are general I/O ports, the
function can be switched with PFDDR.
The PF0 pin functions as a bus control input pin
(WAIT) when the appropriate bus controller
settings are made. Otherwise, PF0 is an I/O port
and the function can be switched with PF0DDR.
Section 11 I/O Ports
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