R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 433

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin
high level sampling has been completed by the time the DMA write cycle ends, acceptance
resumes after the end of the write cycle, DREQ pin low level sampling is performed again, and
this operation is repeated until the transfer ends.
Figure 8.28 shows an example of block transfer mode transfer activated by the DREQ pin falling
edge.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
φ
DREQ
Address
bus
DMA
control
Channel
Figure 8.28 Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer
[1]
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts.
[4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the dead cycle
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Idle
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)
Minimum of 4 cycles
[1]
Bus release
Request
[2]
Read
[3]
Transfer source
DMA read
Request clear period
Write
1 block transfer
Transfer destination
DMA write
Acceptance resumes
Dead
Minimum of 4 cycles
[4]
Request
DMA
dead
Idle
[5]
release
Bus
Read
[6]
Transfer source
DMA read
Write
Request clear period
1 block transfer
Section 8 DMA Controller (DMAC)
Transfer destination
DMA write
Dead
Acceptance resumes
DMA
dead
Page 403 of 1448
[7]
Idle
Bus release