R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 1053

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
No
No
No
Write transmit data in ICDRT
Write transmit data in ICDRT
No
No
No
Read ACKBR in ICIER
Set MST = 0 and TRS
Read BBSY in ICCRB
Set MST = 1 and TRS
Read TDRE in ICSR
Read TEND in ICSR
Clear TEND in ICSR
Clear STOP in ICSR
Read STOP in ICSR
Clear TDRE in ICSR
Read TEND in ICSR
Write transmit data
Write BBSY = 1
Write BBSY = 0
= 0 in ICCRA
= 1 in ICCRA.
and SCP = 0.
Figure 17.14 Sample Flowchart for Master Transmit Mode
and SCP = 0
ACKBR=0 ?
Final byte?
BBSY=0 ?
TEND=1 ?
TDRE=1 ?
TEND=1 ?
STOP=1 ?
in ICDRT
Transmit
Initialize
mode?
Start
End
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
Master receive mode
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] Wait for the completion of transmission for the final byte.
[11] Clear TEND flag.
[12] Clear STOP flag.
[13] Stop condition issuance.
[14] Wait for the generation of the stop condition.
[15] Set slave receive mode. Clear TDRE.
Test the status of the SCL and SDA lines.
Select master transmit mode.
Start condition issuance.
Select transmit data for the first byte (slave address + R/W).
Wait for 1 byte to be transmitted.
Test the acknowledge bit, transferred from the specified slave device.
Set transmit data for the second and subsequent data (except for the final byte).
Wait for ICDRT empty.
Set the final byte of transmit data.
Section 17 I
2
C Bus Interface 2 (IIC2)
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