R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 1014
R4F24278NVFQU
Manufacturer Part Number
R4F24278NVFQU
Description
MCU 512K/48K 2.7-5.5V 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet
1.R4F24278NVFQU.pdf
(1482 pages)
Specifications of R4F24278NVFQU
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R4F24278NVFQU
Manufacturer:
REALTEK
Quantity:
2 300
Company:
Part Number:
R4F24278NVFQU
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 16 Serial Communication Interface (SCI, IrDA, CRC)
16.10.7 Operation in Case of Mode Transition
(1)
(2)
Receive operation should be stopped (by clearing RE to 0) before setting the module stop state or
making a transition to software standby mode. RSR, RDR, and SSR are reset. If a transition is
made during reception, the data being received will be invalid.
To continue receiving without changing the receive mode after the relevant mode is cleared, set
the RE bit to 1 before starting reception. To receive in a different receive mode after clearing the
relevant mode, the procedure must be started again from initialization.
Figure 16.39 shows a sample flowchart for mode transition during reception.
Page 984 of 1448
Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before setting the module
stop state or making a transition to software standby mode. TSR, TDR, and SSR are reset. The
output pin states in the module stop state or software standby mode depend on the port
settings, and become high-level output after the relevant mode is cleared. If a transition is
made during transmission, the data being transmitted will be undefined.
When transmitting without changing the transmit mode after the relevant mode is cleared,
transmission can be started by setting TE to 1 again, and performing the following sequence:
SSR read → TDR write → TDRE clearance. To transmit with a different transmit mode after
clearing the relevant mode, the procedure must be started again from initialization.
Figure 16.36 shows a sample flowchart for mode transition during transmission. Port pin states
during mode transition are shown in figures 16.37 and 16.38.
Operation should also be stopped (by clearing TE, TIE, and TEIE to 0) before making a
transition from transmission by DTC transfer to module stop state setting or software standby
mode transition. To perform transmission with the DTC after the relevant mode is cleared,
setting TE and TIE to 1 will set the TXI flag and start DTC transmission.
Transmission
Reception
H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
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